Electrical computers and digital processing systems: multicomput – Network-to-computer interfacing
Reexamination Certificate
1999-01-12
2002-06-11
Vu, Viet D. (Department: 2154)
Electrical computers and digital processing systems: multicomput
Network-to-computer interfacing
C709S241000, C710S052000, C710S060000
Reexamination Certificate
active
06405260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to a data transmission apparatus for transmitting a data between a microcomputer and a main system, and a method thereof, and in particular to a data transmission apparatus capable of applying a low-priced microcomputer to a main system which is not provided with a logic circuit performing an interface with the main system, and of improving a transmission speed by increasing a size of the data that can be processed at a time, and a method thereof.
2. Description of the Background Art
In general, in order to transmit a data between a microcomputer and a main system, the microcomputer includes: a system control register for controlling a chip operation; a host interface control register for controlling a host interface interrupt and fast address (fast A
20
) gate functions; an input data register and an output data register for carrying out a read/write operation on a processor; a state register for communicating state information during a host interface processing; and a serial/timer control register for controlling a bus interface and a host interface, controlling an operational mode, and selecting a clock source from a timer. In addition, the microcomputer is controlled by external signals, such as a host interface read signal, a host interface write signal, a host interface selection signal for the input data register, the output data register and the state register, and an address gate control signal A
20
.
Here, only the essential units of the microcomputer for performing a data transmission with the main system will now be described.
FIG. 1
is a block diagram illustrating a structure for transmitting the data between the main system
10
and the microcomputer
20
. As shown therein, the microcomputer
20
is provided with a state register
21
storing the state information during the interface processing; the input data register
22
to which the information on a data bus
1
is inputted; and the output data register
23
outputting the stored information to the data bus
1
.
The data transmission process between the microcomputer
20
and the main system
10
will now be schematically explained.
First, in order to transmit the information from the main system
10
to the microcomputer
20
, when the chip selection signal/CS is low, an input buffer full signal IBF, which is a flag signal, is set at a rising edge of a write control signal/IOW, and the information on the data bus is written on the input data register
22
.
On the other hand, in order to transmit the information from the microcomputer
20
to the main system
10
, an output buffer full signal OBF, which is a flag signal is cleared at a rising edge of the read control signal/IOR, thereby reading the information stored in the output data register
23
and loading it to the data bus.
Here, an address signal A
0
is latched in a fourth bit of the state register
21
in order to determine whether the written information is a command or a data. That is, when the fourth bit of the state register
21
is “0”, the information written on the input data register
22
is the data. In the case that the fourth bit thereof is “1”, the information is the command.
The above-described process according to the states of the external signals will now be explained in detail.
First, when the address signal/A
0
, the chip selection signal/CS and the read control signal/IOR are low, and the write control signal/IOW is high, the data is read from the output data register
23
. In the case that the address signal/A
0
is high, the state is read from the state register
21
.
On the other hand, when the chip selection signal/CS, the write control signal/IOW and the address signal/A
0
are low, and the read control signal/IOR is high, the data is written on the input data register
22
. In the same condition, when the address signal/A
0
is high, the command is written thereon.
When the microcomputer
20
is a single-chip microcomputer provided with a register for internally storing a data and a register for storing a command, there is a disadvantage in that chip size and production cost of the microcomputer
20
are increased.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a data transmission method and apparatus for transmitting a data between a main system and a low-priced microcomputer, which is not provided with a logic circuit capable of performing an interface with the main system, sensing both the main system and the microcomputer by using an error sensing bit in order to sense a problem in transmission, and is capable of improving a transmission speed by increasing a size of the data to be processed at a time.
In order to achieve the above-described object of the present invention, there is provide a data transmission apparatus for transmitting a data between a main system and a microcomputer which is not provided with a logic circuit performing an interface with the main system, including: a signal controller sensing data transmission and generating first and second transmission control signals; a data transmission detector communicating the data transmission to the microcomputer pursuant to the first transmission control signal from the signal controller; and a double buffer latching the data for a predetermined period in order for the main system or microcomputer to read through a corresponding port the data to be transmitted according to the first and second transmission control signals from the signal controller.
In order to achieve the object of the present invention, there is also provided a data transmission method for transmitting a data between a main system and a microcomputer, including: a first transmission step having: a first step for the microcomputer confirming whether a command or data is exactly received and transmitting a request data to the main system to transmit a next-succeeding command or data, when the command or data is partially transmitted from the main system to the microcomputer; and a second step for the microcomputer confirming whether the entire command or data is exactly received and transmitting a first confirmation data to the main system, when the main system receives the request data and transmits the residual command or data to the microcomputer; and a second transmission step having: a third step for the microcomputer receiving a data transmission request data and partially transmitting the data to the main system, when the main system transmits the data transmission request data to the microcomputer; and a fourth step for the microcomputer receiving a second confirmation data and transmitting the residual data to the main system, when the main system confirms whether the transmitted data is exactly received and transmits the second confirmation data to the microcomputer in order to transmit a next-succeeding data.
REFERENCES:
patent: 3979732 (1976-09-01), Hepworth et al.
patent: 4485470 (1984-11-01), Reali
patent: 4860283 (1989-08-01), Takano et al.
patent: 5386585 (1995-01-01), Traylor
patent: 5507001 (1996-04-01), Nishikawa
patent: 5790567 (1998-08-01), Bolotin et al.
Kang Jae-Sik
Kim Yang-Hoon
Birch & Stewart Kolasch & Birch, LLP
LG Electronics Inc.
Vu Viet D.
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