Pulse or digital communications – Synchronizers – Synchronization failure prevention
Reexamination Certificate
1999-03-23
2001-08-14
Le, Amanda T. (Department: 2034)
Pulse or digital communications
Synchronizers
Synchronization failure prevention
C370S505000, C370S517000, C327S161000
Reexamination Certificate
active
06275550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transmission device capable of carrying out clock correction independent from transfer rate, and realizing both normal data reception and speed-up of the data transmission.
2. Description of the Related Art
FIG. 1
is a block diagram showing a configuration of a conventional data transmission device described in Japanese Patent Application Laid-open No.S61-7756. In the following description, N represents an integer showing a divided frequency ratio of a clock and n represents an integer showing the upper limit of the divided frequency ratio determined by a system configuration of the data transmission device.
The conventional data transmission device comprises a data transmission circuit
101
, an external interface circuit
102
, a transmission clock frequency divider circuit
103
, a reception clock frequency divider circuit
104
, and a data transition detection circuit
105
. The data transmission circuit
101
includes a function for receiving data input to a reception serial data
302
by a reception data shift clock
306
, and a function for transmitting data to a reception serial data
301
by a reception data shift clock
304
. The data transmission circuit
101
outputs a divided frequency ratio selection signal
309
(N=1 to n) based on transfer rate (½ of a basic clock
303
) previously determined between this data transmission device and a target of the transmission external to the data transmission device. The external interface circuit
102
includes an interface function with external to the data transmission device. The transmission clock frequency divider circuit
103
and the reception clock frequency divider circuit
104
divide the basic clock
303
based on the divided frequency selection signal
309
which is input, and outputs the transmission data shift clock
304
and the reception data shift clock
306
. The transmission data shift clock
304
is input to a terminal of the data transmission circuit
101
. The reception data shift clock
306
is input to a terminal of the data transmission circuit
101
.
As shown in
FIG. 2
, the reception clock frequency divider circuit
104
includes an AND gate
529
for controlling the input of the basic clock
303
, an n-stage connection T-type flip-flop
517
for dividing the basic clock
303
, an n-input selector
519
for selecting the reception data shift clock output from the reception clock frequency divider circuit
104
, and a reception bit number counter
528
for counting the reception clock number. The n-stage connection T-type flip-flop
517
is arranged to be initialized if the reception clock frequency divider circuit initializing signal
310
is input to an initializing terminal RD. The data transition detection circuit
105
includes a function for outputting the reception clock frequency divider circuit initializing signal
310
if the data transition in the reception serial data
302
is detected.
Next, the operation of the conventional data transmission device will be explained with reference to a timing chart in FIG.
3
.
FIG. 3
shows the operation timing at the time of reception when the reception data shift clock
306
is set to be ⅛ of the basic clock
303
. At the time of reception, there are two kinds of operation states. When there is no variation in the reception serial data
302
, the reception clock frequency divider circuit
104
simply divides the basic clock
303
and supplies the reception data shift clock
306
to the data transmission circuit
101
, whereby the data transmission circuit
101
latches the reception serial data
302
in synchronous with the rising edge of the reception data shift clock
306
.
When there is a variation in the reception serial data
302
, the data transition detection circuit
105
detects the data transition, and outputs the reception clock frequency divider circuit initializing signal
310
. The reception clock frequency divider circuit
104
receives the reception clock frequency divider circuit initializing signal
310
and once initializes the division of the clock. Thereafter, if the reception clock frequency divider circuit initializing signal
310
falls, the reception clock frequency divider circuit
104
again starts the division of the clock and again supplies the reception data shift clock
306
to the data transmission circuit
101
, whereby the data transmission circuit
101
again starts the latching of the reception serial data in synchronous with the rising edge of the reception data shift clock
306
. The latch timing of the data transmission circuit
101
when there is a variation in the reception serial data
302
is always corrected to an intermediate value of the bit length of the reception serial data
302
.
FIG. 4
shows the operation timing at the time of reception when the reception data shift clock
306
is set to ½ of the basic clock
303
. At the time of the setting, if the initialization is carried out due to the reception clock frequency divider circuit initializing signal
310
when the length of the pulse width of the reception clock frequency divider circuit initializing signal
310
is ½ period of the basic clock
303
and in a section where the reception data shift clock
306
is of logic level “1”, the counting operation is adversely started again immediately on the rising edge of the basic clock
303
immediately after the n-stage connection T-type flip-flop
517
is initialized, and there is a possibility that the reception data shift clock
306
is not divided. That is, the clock correction to shorten the clock is erroneously generated and there is a possibility that a normal receiving operation can not be carried out in the data transmission circuit
101
.
To avoid such a problem, if the pulse width o the reception clock frequency divider circuit initializing signal
310
is elongated to the length of one cyclic period of the basic clock
303
, there is an adverse possibility that the rising edge timing of the ½ clock is not varied even if the initialization is carried out due to the reception clock frequency divider circuit initializing signal
310
. That is, there is a timing in which the clock is not corrected, and there is a possibility that a normal receiving operation can not be carried out in the data transmission circuit
101
.
Further, if the pulse width o the reception clock frequency divider circuit initializing signal
310
is elongated to the length of one cyclic period of the basic clock
303
, the stopping period of the n-stage connection T-type flip-flop
517
at the time of initialization due to the reception clock frequency divider circuit initializing signal
310
becomes too long, the clock correction to elongate the clock is erroneously generated, the latching timing of the reception data is lost, and there is a possibility that a normal receiving operation can not be carried out in the data transmission circuit
101
.
These problems are caused by the following reasons. That is, according to the configuration of the conventional data transmission device, since the correction of the reception data shift clock is carried out by the initialization of the divider, when the dividing ratio of the reception data shift clock with respect to the basic clock is low, the initializing operation is not carried out depending upon the timing of the dividing operation and the initializing operation, or the initializing operation is generated at an erroneous timing with respect to the reception data, the clock correction operation is not effectively carried out, and a normal receiving operation an not be carried out.
More particularly, in the conventional data transmission device, as described above, when the reception data shift clock supplied to the data transmission circuit is ½ of the basic clock, the initialization of the reception data shift clock frequency divider is not normally carried out, or the clock shortening operation or the clock elongating opera
Foley & Lardner
Le Amanda T.
NEC Corporation
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