Pulse or digital communications – Systems using alternating or pulsating current – Antinoise or distortion
Reexamination Certificate
1999-12-30
2002-10-29
Le, Amanda T. (Department: 2734)
Pulse or digital communications
Systems using alternating or pulsating current
Antinoise or distortion
C375S354000, C327S142000, C327S161000, C365S189050, C365S189110, C365S194000, C365S198000, C365S206000
Reexamination Certificate
active
06473468
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transmission device using a pulse generating device, and in particular to an improved data transmission device which can prevent a mis-operation in a high speed operation, and reduce noise generation in a low speed operation, by detecting a period of an externally-inputted clock signal, and controlling a pulse width of a pulse signal generated in a device according to the period.
2. Description of the Background Art
In general, a synchronous dynamic random access memory (DRAM) controls an input/output of a data, synchronized with an externally-inputted clock signal CLK, and thus internal signals are regularly generated according to the clock signal.
FIG. 1
is a circuit diagram illustrating a conventional data transmission device. As shown therein, the data transmission device includes: a data bus line sense amp
2
operated according to a data sense amp enable signal EN which is a pulse signal having a predetermined pulse width; first and second inverters IN
1
, IN
2
respectively inverting outputs from the data bus line sense amp
2
; first and second pull-down drivers
4
,
6
respectively performing a pull-down operation on read data lines RD, /RD according to outputs from the first and second inverters IN
1
, IN
2
; first and second delay units DE
1
, DE
2
respectively delaying pulse data from the read data lines RD, /RD for a predetermined time; first and second pull-up drivers
8
,
10
controlled according to outputs from the first and second delay units DE
1
, DE
2
, for respectively resetting the read data lines RD, /RD at a high level after a predetermined time from the time when the pulse data are applied to the read data lines RD, /RD; and a data output unit
12
buffering and externally outputting the data applied to the read data lines RD, /RD.
The data output unit
12
consists of a third inverter INV
3
and a fourth inverter INV
4
which are connected to the read data lines RD, /RD, respectively.
Here, the data bus sense amp enable signal EN which is an internal pulse signal having a predetermined pulse width is generated by a conventional pulse generating device as shown in
FIG. 2
a
or
2
b.
That is, the pulse generating device includes: a delay unit DE delaying the externally-inputted clock signal CLK for a predetermined time; and a NAND gate ND or a NOR gate NOR generating a pulse signal by NANDing or NORing an output signal from the delay unit DE and the clock signal CLK, thereby outputting an internal pulse signal EN having a predetermined pulse width.
However, a pulse width of a signal generated by the pulse generating device is determined according to the delay time of the delay unit DE, and thus the pulse generating device generates a pulse signal having a pulse width as long as the delay time.
The operation of the conventional data transmission device will now be explained.
The data applied to local data bus lines LDB, /LDB are inputted to the data bus line sense amp
2
. When the data bus line sense amp
2
is operated according to the data bus line sense amp enable signal EN, and outputs an output signal, the pull-down drivers
4
,
6
are driven by the output signal, thereby transmitting the pulse data to the read data lines RD, /RD.
The data applied to the read data lines RD, /RD drive the succeeding pull-up drivers
8
,
10
after a predetermined delay time, thereby resetting the read data lines RD, /RD.
The conventional data transmission device has a disadvantage in that the delay time of the delay units DE
1
, DE
2
controlling the pull-up drivers
8
,
10
is fixed, and thus the pulse width of the pulse signal outputted through the read data lines RD, /RD is also fixed.
Accordingly, when the delay time is set longer in a high frequency operation, if data having an identical phase are consecutively inputted, a margin between two pulse data signals is not obtained, thus causing a mis-operation that the data line is not resetted.
In addition, in case the delay time is too short in a low frequency operation, although an operational speed is low, a large amount of current is consumed for a short time in the data transmission, and thus a noise is generated.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a data transmission device which can selectively transmit a data signal according to a high/low frequency by detecting a period of a clock signal, and receiving as a control signal an output signal from a pulse generating device controlling a pulse width according to the period.
In order to achieve the above-described object of the present invention, there is provided a data transmission device including: a data bus sense amp controlled according to a control signal which is a pulse signal, for detecting and amplifying a data applied to a data bus; a plurality of driving units for buffering and outputting an output from the data bus sense amp; a read data line receiving a pulse data transmitted by the plurality of driving units; a plurality of pull-down units controlled according to an output signal from the plurality of driving units, for performing a pull-down operation on the read data line; a plurality of multi-delay units controlled according to a detection signal detecting a period of an externally-inputted clock signal, for delaying the pulse data applied to the read data line for a different delay time; and a pull-up unit controlled according to an output signal from the plurality of multi-delay units, for resetting the data line.
REFERENCES:
patent: 5384552 (1995-01-01), Iwasaki
patent: 5519729 (1996-05-01), Jurisch et al.
patent: 5526332 (1996-06-01), Yamada et al.
patent: 5657361 (1997-08-01), Inagaki et al.
patent: 5798969 (1998-08-01), Yoo et al.
patent: 5917353 (1999-06-01), Teel
patent: 6329857 (2001-12-01), Fletcher
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Le Amanda T.
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