Data transmission circuit having decreased parasitic capacitance

Details Data transmission circuit having decreased parasitic capacitance Data transmission circuit having decreased parasitic capacitance

1987-06-29

1988-07-12

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307582, 307242, H03K 19096, H03K 1716, H03K 17687, H03K 1756

Patent

active

047572159

ABSTRACT:
A data transmission circuit for CMOS dynamic random access memory devices having a data input buffer for converting TTL input data signals to CMOS logic level data signals and providing true and complement data signals on a pair of data bus lines, a pair of transmission gates for transmitting the true and complement data signals to a pair of true and complement I/O bus lines comprising a pair of similar constitutional I/O bus line pull-up or pull-down circuits between the output lines of the transmission gates and the I/O bus lines for making logic operations on the data bus lines. The I/O bus lines alternate at the time of a writing operation and a I/O bus line equalizing circuit is connected between the true and complement I/O bus lines for equalizing the pair of the I/O bus lines at a high speed, before or after a writing cycle.

REFERENCES:
patent: 4429374 (1984-01-01), Tanimura

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