Data transmission circuit for checking of memory device

Details Data transmission circuit for checking of memory device Data transmission circuit for checking of memory device

1993-11-29

1996-08-13

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

055464076

ABSTRACT:
The pattern data a, b, . . . , m, which are different data, for checking a memory device, are supplied to a data selector 3 of the data selecting circuit 2 through the flip-flop FF1A. The AND circuits 5A and 5B output set clock signals S11 and S12 on the basis of the register switching signal S8 and the register set signal S7. Also, the registers 6A and 6B latch the data selecting signal S9 with the set clock signals S11 and S12 respectively, and output select instructions (data selecting signals S13 and S14) for selecting the different pattern data. When the selector 7 receives the data switching signal S5 which is latched with the time clock signal S3 of the flip-flop FF1A in the flip-flop FF1B, the data selector 7 outputs the data selecting signal S15, which then alternately becomes either the data selecting signal S13 or the data selecting signal S14, to the data selector 3. As a result, the data selector 3 alternately outputs two different pattern data to a testing pin which is attached to an electric terminal of the memory device.

REFERENCES:
patent: 5072447 (1991-12-01), Perloff et al.

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