Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1994-06-15
1996-05-07
Nelms, David C.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518911, 36518906, 36523008, G11C 700
Patent
active
055153348
ABSTRACT:
In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
REFERENCES:
patent: 5200921 (1993-04-01), Okajima
patent: 5331593 (1994-07-01), Merritt et al.
patent: 5355343 (1994-10-01), Shu et al.
Agata Masashi
Akamatsu Hironori
Iwanari Shunichi
Kikukawa Hirohito
Kotani Hisakazu
Le Vu A.
Matsushita Electric - Industrial Co., Ltd.
Nelms David C.
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