Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1995-12-15
1997-10-21
Nelms, David C.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518911, 365190, 327309, 327318, H03K 326
Patent
active
056803664
ABSTRACT:
In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.
REFERENCES:
patent: 4972517 (1990-11-01), Kondou et al.
patent: 5218248 (1993-06-01), Nagao
patent: 5347183 (1994-09-01), Phelan
Agata Masashi
Akamatsu Hironori
Iwanari Shunichi
Kikukawa Hirohito
Kotani Hisakazu
Le Vu A.
Matsushita Electric - Industrial Co., Ltd.
Nelms David C.
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