Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-01-19
2001-04-10
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S201000, C327S203000, C327S208000
Reexamination Certificate
active
06215344
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a data transmission circuit for connecting an output circuit for outputting data to an input circuit to which input data is supplied, and more particularly to a data transmission circuit used in a semiconductor integrated circuit of a data path and a memory, etc.
FIG. 7
is a circuit diagram showing a conventional data transmission circuit.
The data transmission circuit illustrated in
FIG. 7
is constructed of an inverter INV and a clocked inverter CKINV that are serially connected between an output circuit
1
for outputting data and an input circuit
2
for receiving data, and an output capacitance Cout connected between an output node a of the inverter INV and a potential node Vss.
Control signals CNT and /CNT (the symbol “/” prefixed to the signal name hereinafter implies a logical inversion) are supplied to the clocked inverter CKINV, whereby the data transmission circuit is switched ON/OFF according to the necessity. The data is thus transmitted between the output circuit
1
and the input circuit
2
.
In the conventional data transmission circuit shown in
FIG. 7
, however, a voltage applied to the node a oscillates at a full amplitude with the data output from the inverter INV, and the electric power consumed in the data transmission circuit is proportional to a square of a voltage amplitude. Accordingly, if an activation rate of the data outputted from the output circuit
1
is high, the problem is that a charging/discharging process at the output capacitance Cout is repeated, which leads to a consumption of large electric power.
Furthermore, the control signal CNT becomes “0”, and accordingly the data transmission circuit is switched OFF, at which time an electric potential of an output node b of the clocked inverter CKINV, i.e., the electric potential of an input node b of the input circuit
2
comes to an electric potential between a “1” level signal potential and a “0” level signal potential of the data signal with the result that the node b is brought into a floating state. As a result, a through-current flows between a first power source potential node Vdd and a potential node Vss of an input gate circuit within the input circuit
2
, and, because of a multiplicity of data transmission circuits being used in the semiconductor integrated circuit of the data path and the memory etc, this causes an increase in the consumption of the electric power.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a data transmission circuit requiring a low quantity of consumed electric power.
According to the present invention, there is provided a data transmission circuit comprising:
a push-pull circuit including first and second MOS transistors, connected in series between a first first power source potential node and a second power source potential node, to which a first data signal and a second data signal defined as an inverted signal of the first data signal are respectively supplied;
an output capacitance connected between the second power source node and a connecting node between said first MOS transistor and said second MOS transistor which serves as an output node of said push-pull circuit;
a transfer gate connected to the output node of said push-pull circuit;
a first inverter connected to the output node of said transfer gate; and
a second inverter connected to said first inverter to form a feedback loop.
In a case where scan flip-flops and data transmission circuits are provided at a plurality of stages, when an output data signal of a push-pull circuit at each stage is changed into a scan input data signal of the scan flip-flop at the next stage, it is possible to reduce the consumed electric power by decreasing an amplitude of an output node potential of the push-pull circuit on the occasion of a storage operation and a delay operation of the scan flip-flop in a normal mode. In a scan mode, the output node potential of the push-pull circuit takes a full amplitude, the scan operation can be thereby performed while preventing a through-current from flowing due to a floating state of the node to which a scan input data signal is inputted.
REFERENCES:
patent: 4820939 (1989-04-01), Sowell et al.
patent: 4894803 (1990-01-01), Aizaki
patent: 5729172 (1998-03-01), Tsukada
patent: 5812002 (1998-09-01), Yoshida
patent: 5831463 (1998-11-01), Sachdev
patent: 5905393 (1999-05-01), Rinderknecht et al.
patent: 5912937 (1999-06-01), Goetting et al.
Higashi Tatsuya
Nogami Kazutaka
Callahan Timothy P.
Kabushiki Kaisha Toshiba
Luu An T.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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