Pulse or digital communications – Systems using alternating or pulsating current
Patent
1997-09-02
2000-06-20
Chin, Stephen
Pulse or digital communications
Systems using alternating or pulsating current
375214, 375288, 713400, 713503, H04L 2700
Patent
active
06078623&
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to an apparatus and a method for data transmission as well as to a parallel processor system using the apparatus and the method. More particularly, the invention relates to an apparatus and a method for parallelly transmitting a plurality of bits of data and a parallel processor system utilizing the apparatus and the method.
Conventional processor systems each includes a plurality of processors that transmit data between the component processors typically using one of the following two data transmission methods:
The first method involves transmitting data in complete synchronism with a system clock, commonly adopted by processor systems. FIG. 2 is a block diagram of a conventional data transmission setup using the first data transmission method. In a processor system of FIG. 2, reference numeral 200 stands for a transmitting-side LSI, 210 for a printed circuit board carrying the LSI 200, 250 for a receiving-side LSI, and 260 for a printed circuit board carrying the LSI 250. With the first data transmission method in use, the process system includes a single generator 290. The generator 290 generates a system clock signal that is distributed via clock buffer gates 291 through 296 (part of the distribution section) to flip-flop groups 201 and 251 on a low-skew basis inside the processor system. It is necessary for data transmission to take place between the flip-flops over transmission lines 280 exactly n times the system clock cycle (i.e., machine cycle). This requires designing the transmission lines so as to control strictly the amount of delay over the lines between the transmitting-side flip-flop group 201 and the receiving-side flip-flop group 251 (including logic gate groups 202 and 252 on the lines). The processor system is actually built on the basis of that design. If the data transmission time exceeds one machine cycle, it is imperative to devise a transmission line design to meet two requirements: that a maximum calculated delay time should fall within n machine cycles when the calculations take into account the system clock skew and the propagation time differences stemming from manufacturing variations of semiconductors constituting the transmission lines; and that a minimum calculated delay amount should exceed (n-1) machine cycles when the calculations take into account the hold time of the receiving-side flip-flops. Below are typical expressions by which to make the calculations for the setup in FIG. 2:
Maximum delay time, obtained by
Minimum delay time, acquired by group 251, depicted in FIG. 15.
The second data transmission method conventionally utilized works typically as follows: the transmitting side transmits data to the receiving side together with a clock signal synchronized with the data, while the receiving side receives the data in keeping with the transmitted clock signal and places the received data into registers from which the data are moved to other registers in synchronism with a receiving-side clock signal. A typical setup of the second method is shown in FIG. 3. Inside a transmitting-side LSI 300, a flip-flop group 301 is supplied with a transmitting-side clock signal. The same clock signal is also sent along with data to a receiving-side LSI 350 via an output buffer gate 303 and a clock transmission line 381. On the receiving side, a flip-flop group 351 is fed with both the data sent over data transmission lines 380 and the clock signal transmitted via a buffer gate 353. The data are held by the flip-flop circuit 351 in keeping with the simultaneously transmitted clock signal. The transmitting-side LSI 300 is mounted on a printed circuit board 310 and the receiving-side LSI 350 on a printed circuit board 360. Buffer gates 302 and 352 are used for data transmission. Reference numerals 391 through 393 and 396 through 398 denote clock buffer gates.
Circuits inside the receiving-side LSI 350 operate on a clock signal from a generator 395 furnished separately from the transmitting-side clock generator 390. To transmit data to the registers operati
REFERENCES:
patent: 4878219 (1989-10-01), Kaufman et al.
patent: 4881165 (1989-11-01), Sager et al.
patent: 4945548 (1990-07-01), Iannarone et al.
patent: 5623944 (1997-04-01), Self et al.
Fujita Bunichi
Isobe Tadaaki
Chin Stephen
Hitachi , Ltd.
Jiang Lenny
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