Data transferring system with multiple port bus connecting the l

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Details

395440, G06F 938, G06F 1300

Patent

active

056896700

ABSTRACT:
A data processing system using a prefetch mechanism with high speed cache memory to increase the processing speed. Data is prefetched from a low speed main memory to the cache memory for data transfer instructions via multiple ports. For a program control transfer instruction, the prefetch mechanism prefetches instruction for each possible program path, stores them in the cache memory and continues with the prefetch processes.

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