Amusement devices: games – Including means for processing electronic data – Data storage or retrieval
Patent
1996-07-19
1998-10-06
Manuel, George
Amusement devices: games
Including means for processing electronic data
Data storage or retrieval
395823, G06F 1200
Patent
active
058169210
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a data transferring device. More particularly, it relates to a device, which transmits and receives data through data buses between a plurality of data transmitters. A data transmitting and receiving device is here defined as a circuit device, which can send out to and receive the data from the data buses. Therefore, a memory device may be also considered as a data transmitting and receiving device. Further, the present invention relates to a data transferring device, which can continuously transfer data read out from the memory device. Furthermore, the present invention relates to a data transferring device to write data from a byte boundary to the memory device. Additionally, it relates to a video game apparatus employing the above-described transferring device.
BACKGROUND OF THE INVENTION
Data processing equipment, such as a video game apparatus, i.e., an information processing apparatus, includes a plurality of functional circuits, each of which is assigned to perform a specific function and has a data transmitting and receiving device as defined above.
It is necessary to transmit and receive data with a high speed between a plurality of data transmitting and receiving devices, for example, between a CPU and a memory device.
Therefore, a plurality of CPUS, memory devices, or the like, as data transmitting and receiving devices are connected to a data bus. Data transmitting is performed via the data buses between the data transmitting and receiving devices. In a conventional system for transmitting addresses via the buses, all of data transmitting and receiving devices, such as a CPU, a RAM, and a VDP (video display processor), are connected to one data bus.
Therefore, in the conventional system having such a structure as the above, data existing on the data bus should be only one at a certain timing to prevent from collision of data.
Accordingly, it becomes a problem not to concurrently transfer various kinds of data between, for example, a CPU and a RAM, and an external memory and a VDP. Further, when there are differences between bus sizes, with which data transmitting and receiving devices can interface, each data transmitting and receiving device should have an own interface circuit to interface with a common bus, that is, a CPU bus.
On the other hand, in a video game apparatus, i.e., a data processor or an information processing apparatus, an external storage, that is, a memory cartridge is detachably connected to a console unit of the video game apparatus, and data read out from the memory cartridge is transferred to the console unit via a bus.
In recent years, a processing speed of CPUs has been increased, and consequently, the speed of transferring data in a system has also become fast.
In such a case, however, it should be considered that the high speed of transferring data causes leakage of impediment radio waves to the outside. FCC (Federal Communication Commission), or the like, has predetermined a standard to regulate the leakage of the impediment radio waves.
Therefore, it becomes a problem not to make a high speed in transferring data on the bus to the console unit from an external storage device, which is detachably connected to the console unit, due to such the FCC standard.
Meanwhile, as described above, in a data processor, such as a video game apparatus, it is required that data can be transferred with a high speed between a CPU and a memory, which are considered as a functional circuit.
In this respect, to reduce a functional load on a CPU, it has been introduced to employ a direct memory access device (DMA) for transmitting or transferring data.
FIG. 1 is to explain an operation of a conventional system employing the direct memory access device. FIG. 2 illustrates an operational timing chart for the system of FIG. 1.
FIG. 1 shows a structural example of a video game apparatus, which includes a direct memory access circuit (DMA) 60, a CPU 61 for executing and controlling a game program, a work RAM 62 for storing data durin
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Manuel George
Sega Enterprises Ltd.
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