Patent
1992-09-03
1996-01-02
Knepper, David D.
395375, 395846, G06F 1300
Patent
active
054816777
ABSTRACT:
A data transfer system has an address bus and a data bus, each divided into two parts by a bus switch. A microprocessor and program memory are connected to the first parts of the address and data buses. A data memory, data transfer controller, and input/output devices are connected to the second parts of tile address and data buses. While the microprocessor is fetching an instruction from the program memory, the bus switches disconnect the two parts of the buses, enabling the data transfer controller to transfer data directly between the data memory and input/output devices. At other times the bus switches connect the two parts of the buses, enabling the microprocessor to access the data memory and Input/output devices.
REFERENCES:
patent: 4455620 (1984-06-01), Watanabe
patent: 4847750 (1989-07-01), Daniel
Kai Yoshihide
Tanigawa Hiroya
Wakahara Toshihiko
Knepper David D.
Nippon Telegraph and Telephone Corporation
OKI Electric Industry Co., Ltd.
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