Data transfer system for buffering and selectively manipulating

Details Data transfer system for buffering and selectively manipulating Data transfer system for buffering and selectively manipulating

1995-06-06

1997-03-25

Shah, Alpesh M.

Boots, shoes, and leggings

395853, 395309, 395250, 364240, 364239, 364260, 364DIG1, G06F 1300

Patent

active

056153821

ABSTRACT:
A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.

REFERENCES:
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patent: 5060139 (1991-10-01), Theus
patent: 5255375 (1993-10-01), Crook et al.
patent: 5471632 (1995-11-01), Gavin et al.
patent: 5471638 (1995-11-01), Keeley
patent: 5499385 (1996-03-01), Farmwald et al.

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