Data transfer system for an integrated circuit, capable of short

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327161, 327162, H03L 700

Patent

active

057480184

ABSTRACT:
In a data transfer system for use in an integrated circuit, a data output circuit comprises a D-FF for latching data to be transferred, in synchronism with an external clock signal, an output buffer receiving and outputting the data latched in the D-FF, and another output buffer receiving the external clock signal for outputting a delayed clock signal which is delayed from the external clock signal by a delay amount of the D-FF. On the other hand, a data input circuit including a first D-FF for receiving the data to be transferred outputted from the D-FF of the data output circuit, in synchronism with the delayed clock signal supplied from the D-FF of the data output circuit, and a second D-FF for fetching the data received in the first D-FF, in synchronism with the external clock signal.

REFERENCES:
patent: 5268937 (1993-12-01), Marbot
patent: 5548620 (1996-08-01), Rogers
patent: 5636165 (1997-06-01), Amatangelo et al.
H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, 1990, pp. 343, 358, 359.

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