Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-07-01
2003-08-26
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S100000, C345S212000, C345S213000, C345S214000
Reexamination Certificate
active
06611247
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a matrix display system, and more particularly, to a display data transfer system and method for a matrix display in which multi-level signaling is used for transferring display data needed for image display on a display panel.
Hereinafter, the description is made with reference to a liquid crystal display (LCD). However, other display devices such as electro-luminescence (EL) display, plasma display panel (PDP) or the likes are also suitable for the present invention.
BACKGROUND OF THE INVENTION
In consideration of size, weight, power and so on, thin or flat displays have been developed, including liquid crystal displays, electro-luminescence displays and electro chromic (EC) displays. Generally, such a display comprises a plurality of picture element circuits arranged as a matrix. Each of the picture element circuits is controlled to turn on/off to determine display state of its corresponding pixel.
FIG. 1
is a block diagram showing a conventional active matrix LCD. A LCD panel
100
comprises a plurality of data bus lines X
1
, X
2
, . . . , Xm, a plurality of scan bus lines Y
1
, Y
2
, . . . , Yn, and a plurality of pixels disposed between the data bus lines and scan bus lines. Each of the pixels consists of a liquid crystal cell and a switching element. In this case, the switching element is a thin film transistor (TFT). The TFT is connected between the liquid crystal cell and one of the data bus lines, and it has a gate connected to one of the scan bus lines. A scan driver
10
selects one of the TFTs in a LCD panel
100
and a digital input data driver
20
provides a data driving signal. A voltage signal required by the scan driver
10
and the digital input data driver
20
is provided by a DC-DC and &ggr; voltage generator
30
. A display data required for image display is generated by a digital timing controller
40
through an input interface
50
, and is sent to the digital input data driver
20
via a digital bus
60
.
To achieve higher speed and better performance, it is proposed that only digital signals are used for data driving. However, in a color LCD, R (red), G (green) and B (blue) video signals can be deemed as three parallel data bus signals, and each of the R, G and B color signals has g bits, which determines a resolution of luminescence for a respective color. Therefore, the display data signals can be considered to be carried by a bus consisting of 3×g data lines. As space resolution and luminescence resolution of an image are increased, number of the data lines (i.e., width of the digital bus
60
) is remarkably increased. Relation between bit number of a color LCD and wiring number is shown in Table 1.
TABLE 1
Input Port Number of Data Driver
Bit Number
Wring Number
1
6
18
8
24
2
6
36
8
48
On the other hand, as transfer speed of interface signal or operating speed of system is increased, transfer frequency of the digital bus
60
is enhanced. Transfer frequencies for various resolutions are shown in Table 2.
TABLE 2
Input Port
Number of Data Driver
Resolution
Transfer Frequency (MHz)
1
VGA
25.175
SVGA
40
XGA
65
2
VGA
12.5875
SVGA
20
XGA
32.5
The increased transfer frequency causes a large electromagnetic interference (EMI). The increased width of the digital but
60
not only increases the wiring number, which in turn makes the circuitry complicated and layout of printed circuit board difficult, but also deteriorates the EMI problem.
For example, in a 6-bit XGA notebook computer, data transfer system of the LCD is shown in FIG.
2
. An input interface
50
utilizes a transceiver for low voltage differential signal (LVDS). The transceiver receives a digital input signal and then outputs it to a digital timing controller
40
where it is converted into a digital display data signal and sent to a digital input data driver
20
. Digital data bus lines between the digital timing controller
40
and digital input data driver
20
only carry signals of either logic “0” or “1”. An input terminal of the input interface
50
is connected to a single-port, 65 MHz bus with 18 bit lines. A buffer can be used in the input interface
50
to produce a two-port output to halve the transfer frequency (32.5 MHz), but the bus width is doubled to have 36 data lines, and transfer between the digital timing controller
40
and the digital input data driver
20
is at 32.5 MHz with two ports. In other words, a compromise must be reached between the bus width and the transfer frequency.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to set forth a data transfer system and method for a matrix type display in which data bus lines are decreased, thereby reducing connection wiring between a timing generator and a data driver, and improving circuitry of the display and layout of printed circuit board.
Another object of the present invention is to reduce data transfer frequency of a matrix type display to resolve the EMI problem.
To achieve the above objects, according to the present invention, a data transfer system for a matrix type display includes a multi-level timing controller connected to a multi-level input data driver via a multi-level signal bus. A digital input signal necessary for image display is converted into a multi-level signal display data output by an encoder in the multi-level timing controller, transferred to the multi-level input data driver through the multi-level signal bus, and converted into a data driving signal for a display panel.
In the timing controller, a display data is converted from a digital format into a multi-level format before entering the bus. After the display data passes through the bus, it is converted back into the original digital format in the data driver. By the aid of the multi-level signal, each bus line between the timing controller and the data driver can carry a multi-state data signal. That is, level number of bus signal states is increased, thereby remarkably decreasing wiring between the controller and the data driver and reducing data transfer frequency at the same time.
REFERENCES:
patent: 4872002 (1989-10-01), Stewart et al.
patent: 5900857 (1999-05-01), Kuwata
patent: 5923342 (1999-07-01), Greenwood et al.
patent: 5953002 (1999-09-01), Hirai et al.
patent: 5974464 (1999-10-01), Shin et al.
patent: 6144355 (2000-11-01), Murata et al.
patent: 6246398 (2001-06-01), Koo
Chang Jung-Chung
Chen Yen-Chen
Dinh Duc Q
Himax Technologies Inc.
Hjerpe Richard
Rabin & Berdo P.C.
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