Patent
1997-07-14
1999-03-02
Coleman, Eric
39580001, G06F 1580
Patent
active
058782656
ABSTRACT:
A computer chip includes a plurality of modules interconnected in an on-chip data transfer network configured in a mesh of rings, ring or rings, or polygonal hub topology. The data transfer network includes links or buses and a switchpoint. The links or buses are configured in a ring topology as a ring of rings or polygonal hub with each group of links or bus including a portion which is shared with a portion of another group of links bus. The bus switchpoint is positioned as a hub at the intersection of the ring of rings. The switchpoint is operable to route data from a source to a destination so that the modules are operable to communicate with each other through the links or buses, and the switchpoint. In various embodiments, the modules are coupled to the links or buses and/or the switchpoint. The various modules may be processors, memories or hybrids and may include, or be coupled through, a communication port coupled to one of the links or buses such that the communication port is operable to transmit and receive data on one or more of the groups of links or buses.
REFERENCES:
patent: 4797882 (1989-01-01), Maxemchuk
patent: 4933933 (1990-06-01), Dally et al.
Itano, et al "HIRB: A Hierarchical Ring Bus" University of Tsukuba, Japan, Proceedings of the Nineteenth Annual Hawaii International Conference on System Sciences, 1986, pp. 206-213.
Gustavson, D.B., "Scalable Coherent Interface and Related Standards Projects," IEEE vol. 12, No. 1, pp. 10-22, Feb. 1992.
Cha, et al, "Simulated Behaviour of Large Scale SCI Rings and Tori," Depts. of Engineering and Computer Science, University of Cambridge, United Kingdom, pp. 1-21, Proceedings of 5th IEEE Symposium on Parallel and Distributed Processing, Dallas, Texas, Dec. 1993.
Franklin, et al, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References," IEEE Transactions on Computers, vol. 45, No. 5, May 1996, pp. 552-571.
Barroso, et al, "Performance Evaluation of the Slotted Ring Multiprocessor," IEEE Transactions on Computers, vol. 44, No. 7, Jul. 1995, pp. 878-890.
Bhuyan, et al, "Approximate Analysis of Single and Multiple Ring Networks," IEEE Transactions on Computers, vol. 38, No. 7, Jul. 1989, pp. 1027-1040.
Arden, et al, "Analysis of Chordal Ring Network," IEEE Transactions on Computers, Vo. C-30, No. 4, Apr. 1981, pp. 291-301.
Advanced Micro Devices , Inc.
Coleman Eric
Duff, Jr. Kenneth
Hood Jeffrey C.
Iselin Louis H.
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