Data transfer method in function expansion system

Details Data transfer method in function expansion system Data transfer method in function expansion system

2000-04-20

2004-01-20

Maung, Zarni (Department: 2154)

Electrical computers and digital processing systems: multicomput

Network-to-computer interfacing

C709S201000, C709S203000, C711S145000, C711S158000

Reexamination Certificate

active

06681260

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a function expansion system, and in particular to a data transfer method in a function expansion system in which a plurality of communication interfaces connected to a bus transfer data via a memory connected to a processor.
2. Description of the Related Art
In general, a computer is provided with a plurality of expansion slots to extend its function or performance. For example, when a communication interface card such as a LAN (local-area network) card plugs into an expansion slot of a computer, the computer's ability can be extended to send and receive data through the network.
Referring to
FIG. 1
, such a function expansion system has a plurality of communication interfaces
8
-
1
,
8
-
2
, . . . , connected to a processor
2
and a memory
3
via a bus
100
. Data transfer between two communication interfaces
8
-
1
and
8
-
2
is conducted via the memory
3
under the control of the processor
2
.
In such a function expansion system, data transfer is typically performed such that a communication interface
8
-
1
or
8
-
2
writes received data into the memory
3
and, when finishing the writing operation, the communication interface writes a reception completion notice message into a different area of the memory
3
and then issues an interrupt signal
211
or
212
to the processor
2
.
By an interrupt signal
220
supplied from an interrupt controller
21
in response to the interrupt signal
211
or
212
, software for conducting data reception processing is started in the processor
2
. The software conducts processing on the reception completion notice message, generates a transmission request message, and sends it to the communication interface
8
-
1
or
8
-
2
which should transmit data stored in the memory
3
.
Upon receiving the transmission request message, the communication interface
8
-
1
or
8
-
2
reads data to be transmitted, from the memory
3
and transfers the read data to outside (e.g. LAN). When the data to be transmitted has been completely sent, the communication interface writes a transmission completion message into a different area of the memory
3
, and notifies the processor
2
of the transmission completion by issuing the interrupt signal
211
or
212
to the processor
2
. In
FIG. 1
, reference numeral
4
denotes a processor interface, reference numeral
5
denotes a memory controller, and reference numeral
6
denotes a bus controller.
In the above-described conventional data transfer method, an interrupt signal to the processor is generated every time data is received or transmitted. This results in a problem that processing of other software which is being processed by the processor simultaneously with the data transfer is affected.
Furthermore, since access to the memory is not managed, the following disadvantages are developed. When the processor
2
frequently gains access to the memory
3
, data transfer is likely to be stopped. In the case where the processor is performing high-speed data transfer, processing of other software executed by the processor is affected.
In order to solve these problems, there have been proposed a method of raising the processing speed of the processor
2
, and a method of adding an instruction for processing a multimedia signal to processing instructions of the processor
2
.
So long as such a configuration that an interrupt indicating the reception completion or transmission request issued by a communication interface is processed by software, however, it is impossible to solve such a problem that the software processing is not in time for data transfer increased in speed.
There have been proposed a data processing device allowing high-speed data transfer without software interrupt to a CPU in Japanese Patent Publication No. 4-14378. More specifically, the data transfer processing performed by character control is implemented with hardware, resulting in high-speed transmission/reception data transfer with reduced burden upon the CPU.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a function expansion system and a data transfer method which are capable of reducing the influence of data transfer operation upon the processing performed by software running on a processor.
According to the present invention, a system including a processor; a plurality of communication interfaces connected to a bus, each of which provides an expanded function of the system; and a memory connected to the processor, for storing data received from a first communication interface which is any of the communication interfaces, further includes a scheduler for managing access to the memory by each of the processor and the communication interfaces, and a message converter for converting a reception completion message received from the first communication interface to a transmission request message when determining from the reception completion message that the data having stored in the memory is data to be sent to a second communication interface which is another one of the communication interfaces, wherein the second communication interface reads the data from the memory when receiving the transmission request message.
The message converter preferably generates an interrupt to the processor when determining from the reception completion message that the data having stored in the memory is data to be processed with software running on the processor.
The first communication interface may send the reception completion message to the message converter when the data has been stored into the memory.
The scheduler preferably manages access to the memory by each of the processor and the communication interfaces according to a schedule determined for each of the processor and the communication interfaces. The scheduler may manage access to the memory by each of the processor and the communication interfaces such that a predetermined scheduling period is divided into a plurality of access permission periods, each of which is assigned to one of the processor and the communication interfaces. The predetermined scheduling period may be divided into a plurality of access permission time slices, each of which is assigned to one of the processor and the communication interfaces at predetermined ratios among the processor and the communication interfaces.
The scheduler may give access permission to a communication interface when the processor does not generate an access request to the memory in an access permission time period assigned to the processor.
The scheduler may manage access to the memory by each of the processor and the communication interfaces such that an access request by each of the processor and the communication interfaces is permitted depending on whether number of times the access request has been generated for a predetermined scheduling period is smaller than a predetermined setting value.
As another embodiment, a storage medium is further connected to the bus such that one of the communication interfaces and the storage medium mutually transfer data via the memory.
According to another aspect of the present invention, a method for transferring data from a first communication interface to a second communication interface via the memory, includes the steps of: a) managing access to the memory by each of the processor and the communication interfaces; b) storing data received from the first communication interface into the memory; c) converting a reception completion message received from the first communication interface to a transmission request message when determining from the reception completion message that the data having stored in the memory is data to be sent to the second communication interface; and d) transferring the data from the memory to the second communication interface in response to the transmission request message.
As described above, according to the present invention, access to the memory by each of the processor or each of the communication interfaces is managed by the s

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