Data transfer device and multiprocessor system

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39520001, 395280, G06F 1500

Patent

active

056131380

ABSTRACT:
In a system for executing distribution, arrangement and collection of array data between a host processor and plural processor elements, control parameter regarding array data to be transferred and an identification number assigned to each data receiver are set beforehand to a data receiver of each processor element. Data sequentially sent out onto a data bus with synchronization with a strobe signal from the data transmitter of the host processor are fetched selectively according to a data transfer allowance signal generated based on the control parameter and the identification number. The fetched data is written into a memory with a discrete address.

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