Data transfer device

Details Data transfer device Data transfer device

1994-03-02

1996-03-26

Beausoliel, Jr., Robert W.

Excavating

G08C 2502

Patent

active

055027334

ABSTRACT:
There are provided a data transmitter for sequentially transmitting data to which error correcting codes are added, and a data receiver for returning a retransmission request signal if the received data has errors which cannot be corrected. The data transmitter does not confirm that the retransmission request signal related to the transmitted data is received and data are consecutively transmitted from a FIFO memory in a pipeline fashion while holding the transmitted data in a data latch. The data receiver sequentially stores the received data in the FIFO memory on a receiving end in a pipeline fashion. In the case where the retransmission request signal is transmitted from the data receiver, the data transmitter immediately transmits retransmission data which has been prepared in the data latch.

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Shinji Tomita, Theory of Parallel Computer Structure, Shokodo, pp. 69-99 (1986).
Benelli, "Go-back-N ARQ scheme with buffer at the receiver", IEE Proceedings, vol. 133, Pt. F., No. 3, Jun. 1986, pp. 271-276.

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