Data transfer controlling apparatus for direct memory access

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3649423, 3649472, 364947, 3649511, 364951, 3649446, 364944, 3649705, 3649624, G06F 922, G06F 1202

Patent

active

050180983

ABSTRACT:
A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers, each of which registers stores microaddress information for program processing of the data transfer for a corresponding channel; a second microaddress register which stores microaddress information for program processing other than the program processing of the data transfer; a micro read only memory operatively connected to said first and second microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers and the second microaddress register; and an incremental element operatively connected to said first and second microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers and the second microaddress register, and for writing the incremented microaddress information to the selected one of the first microaddress registers and the second microaddress register; the microaddress information stored in one of the first microaddress registers for the corresponding channel being read out when program processing of data transfer for the corresponding channel is carried out, the microaddress information stored in the second microaddress register being read out when program processing other than the program processing of data transfer is carried out.

REFERENCES:
patent: 3938098 (1976-02-01), Garlic
patent: 3988719 (1976-10-01), Whitby et al.
patent: 4156279 (1979-05-01), Wilhite
patent: 4245305 (1981-01-01), Gechele et al.
patent: 4811306 (1989-03-01), Boning et al.

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