Data transfer controller using dummy signals for continued opera

Details Data transfer controller using dummy signals for continued opera Data transfer controller using dummy signals for continued opera

1990-01-25

1993-11-16

Kulik, Paul V.

Excavating

395425, 371 62, 364DIG1, 3642384, 3642423, 3642435, 3642651, 3642655, 3642676, 3642679, 3642689, G06F 1100, G06F 1328

Patent

active

052631516

ABSTRACT:
In a data processing system, a processor issues a transfer request through a data transfer controller to an extended buffer memory to elicit an accept signal. If the accept signal is not returned from the buffer memory within a specified period, a first dummy signal is generated instead, and the controller notifies this fact to the processor and waits for the return of an advance notice from the buffer memory. If the advance notice is not returned within a specified period, a second dummy signal is generated instead to allow the controller to proceed to transfer data read out of the buffer memory to a main memory. The controller then waits for the return of a status report signal from the buffer memory. If the status report signal is not received within a specified period, a third dummy signal is generated instead to allow the controller to proceed to examine a status signal from the buffer memory to determine whether the transferred data has been correctly read out of the buffer memory. A reply signal is applied to the processor indicating the result of the determination.

REFERENCES:
patent: 4131945 (1978-12-01), Richardson et al.
patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 5091870 (1992-02-01), Datsko et al.

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