Data transfer controller incorporating direct memory access chan

Details Data transfer controller incorporating direct memory access chan Data transfer controller incorporating direct memory access chan

1987-12-15

1992-08-25

Chan, Eddie P.

Boots, shoes, and leggings

364DIG1, 3642383, 364239, 3642391, 3642393, 364240, 3642402, 3642405, 3642419, 3642423, 364284, 3642841, 3642842, G06F 1328

Patent

active

051426722

ABSTRACT:
Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports. Both the DMA channels and I/O ports may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus"). The resulting DTC interface between the Local Bus and a Remote Bus permits a wide performance range of standard peripheral devices to be attached to the RISC system in a manner that does not limit system performance.

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