Data transfer controller and electronic device

Details Data transfer controller and electronic device Data transfer controller and electronic device

2005-01-04

2005-01-04

Ho, Duc (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S423000, C370S475000, C710S022000, C710S305000, C714S054000

Reexamination Certificate

active

06839347

ABSTRACT:
The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. In a data transfer control device in accordance with IEEE 1394, a packet shaping circuit (160) shapes each packet that is transferred in from another node into a form that can be used by an upper layer, and a packet division circuit (180) writes the header of the thus-shaped packet into a header area in RAM and the data thereof into a data area. A data pointer that has been passed from the packet division circuit is appended to the header of the packet during packet shaping. Tags are used to divide packets. Information indicating broadcast information, error status information, and whether or not the packet was received during a self-ID period is appended to the trailer of the packet during the packet shaping. The information, such as ACK, that was appended to the rearmost end of the packet in a time series during packet shaping is written to the start of the header of the packet in RAM.

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“An outline of the IEEE 1394 High Performance Serial Bus” (Interface,Apr. 1996, pp. 1-10).
“Bus Standards for PC Peripheral Equipment” (Interface,Jan. 1997, pp. 106-116).
“Real-Time Transfer Modes and Multimedia-Capable Protocols for IEEE 1394-1995 (FireWire)” (Interface,Jan. 1997, pp. 136-146).

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