Boots – shoes – and leggings
Patent
1993-08-11
1996-06-11
Harrell, Robert B.
Boots, shoes, and leggings
364DIG1, 364DIG2, 3642222, 364229, 3642292, 3642329, 3642385, 364240, 3642419, 364247, 364259, 3642592, 364260, 3642601, 364265, 3642664, 364271, 3642712, 364280, 3642808, 364284, 3642842, 3642844, G06F 15163
Patent
active
055264905
ABSTRACT:
A processor element is provided with a data transfer control circuit that sends out an address count pulse (ACNT) onto a control bus. N data transfer channels each contain a data transfer buffer and a buffer control circuit. The buffer control circuit comprises an identification number register, an input/output control circuit, an address counter, and a comparison circuit. The address counter holds a channel address that is preset in such a way as to allow each channel to take the same channel address number, and increments such a channel address each time it receives the ACNT. If the identification number and the channel address coincide, the data transfer buffer in the same channel is selected. The number of interconnecting wires can be reduced and the transfer of data can be carried out at a high transfer rate, in a multiprocessor system whose linking network between each processor is formed by a series of data transfer channels.
REFERENCES:
patent: 4223380 (1980-09-01), Antonaccio et al.
patent: 4513370 (1985-04-01), Ziv et al.
Harrell Robert B.
Matsushita Electric - Industrial Co., Ltd.
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