Data transfer control unit permitting data access to memory prio

Details Data transfer control unit permitting data access to memory prio Data transfer control unit permitting data access to memory prio

1986-09-30

1989-09-05

Williams, Jr., Archie E.

Boots, shoes, and leggings

3649502, 364957, 364963, 3649632, G06F 1314, G06F 1320, G06F 1328, G06F 1332

Patent

active

048645338

ABSTRACT:
A data transfer control unit comprises a first address register, a second address register and a control circuit. The first address register stores a first final address value of a memory area of a memory into which data is to be transferred. The second address register stores a second final address value of data which has already been transferred to the memory area of the memory. The control circuit compares the first final address value and a second final address value with an address value of data access by a CPU in order to generate a memory indication signal indicative of whether the address value of data accessed by the CPU belongs to the addresses of the data which has already been stored or has not yet been stored. The control circuit further prohibits a data transfer from the memory area to the CPU only when the address value of the data accessed by the CPU belongs to the addresses of the data which have not yet been stored in the memory.

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