Data transfer control system

Details Data transfer control system Data transfer control system

1976-10-27

1979-02-06

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1300, G11C 1900

Patent

active

041387325

ABSTRACT:
A data transfer control system for controlling data transfer between a processor and an input/output device comprises a multi-layer stack for temporarily storing transfer data, such as a first-in first-out stack or a last-in first-out stack; first and second up/down counters having a preset function and permitting any designated address at the stack to be varied; and first and second pointer registers for storing any initially designated address data which is stored in the counter. The first counter permits a direction of a count operation to be determined by the processor and the first point register has an initially designated address data stored therein by the processor. The second counter permits a direction of a count operation to be determined by the input/output device and the second point register has an initially designated address data stored therein by the input/output device. The direction of a data flow at the stack is varied dependent upon the direction in which the first and second counters effect count operations.

REFERENCES:
patent: 3516069 (1970-06-01), Bray et al.
Skov et al., Buffer System, IBM Tech. Disc. Bulletin, vol. 2, No. 5, Feb. 1960, pp. 86-89.

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