Data transfer control method and apparatus for co-processor syst

Details Data transfer control method and apparatus for co-processor syst Data transfer control method and apparatus for co-processor syst

1989-04-14

1992-04-28

Olms, Douglas W.

G06F 100

Patent

active

051093332

ABSTRACT:
A data transfer control apparatus for a co-processor system. The co-processor system includes a memory; a memory bus connected to the memory; a main processor connected to the memory bus and having a control circuit for controlling data read/write relative to the memory, the main processor performing data transfer from/to the memory bus via a first data input/output terminal; and a co-processor connected to the memory bus via a second data input/output terminal. The control apparatus includes a high impedance setting circuit for selectively setting the first data input/output terminal at a high impedance state to electrically isolate the first data input/output terminal from the memory bus; and a control signal generator for selectively outputting a control signal to the high impedance setting circuit to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state. When the co-processor is to perform data read/write relative to the memory, the control signal generator generates the control signal to cause the high impedance setting circuit to set the first data input/output terminal at the high impedance state, and while the first data input/output terminal is set at the high impedance state, the main processor performs read/write control of the memory bus, and the co-processor performs data transfer from/to the memory bus via the second data input/output terminal.

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Intel, Microprocessor and Peripheral.
Motorola, MC 68020 32-bit Microprocessor.

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