Data transfer control device, semiconductor memory device...

Details Data transfer control device, semiconductor memory device... Data transfer control device, semiconductor memory device...

2002-06-26

2003-11-11

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189011, C365S189120

Reexamination Certificate

active

06646947

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer control device for controlling data transfer operations performed between memories, a semiconductor memory device including the same data transfer control device, and an electronic information apparatus including the semiconductor memory device.
2. Description of the Related Art
Conventionally, unlike a memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) which loses data stored therein when turned off, a nonvolatile semiconductor memory device (a nonvolatile memory) is characterized in that data stored in memory cells of the nonvolatile memory is not lost even when turned off. In addition to a flash memory which is now in wide use in mobile phones or the like, examples of the nonvolatile memory include FRAM (Ferro-Electric Random Access Memory) which is recently coming into use in IC cards or the like, MRAM (Magnetic Random Access Memory) which is being intensively developed, etc.
Nonvolatile memory and in particular flash memory are described herein.
Generally, in a flash memory, operation speed of a read operation, a write operation including a verify operation and an erase operation including a verify operation becomes slower for this order of operations. The read operation requires about 100 nanoseconds (nsec), the write operation including a verify operation requires about 30 microseconds (is), and the erase operation including a verify operation requires about 500 milliseconds (msec). That is, in the flash memory, the write and erase operations require extraordinary time as compared to the read operation.
On the other hand, a volatile semiconductor memory device representative of a DRAM and an SRAM is disadvantageous in that stored information is lost when turned off. However, the nonvolatile semiconductor memory device has a feature that a period of time required for the write operation is substantially equivalent to a period of time required for the read operation. For example, an SRAM completes each of the read and write operations in about 100 ns. That is, the SRAM can rewrite data in a period of time which is considerably short as compared to a period of time required for the write or erase operations of the flash memory.
Conventionally, a page buffer technique has been used for compensating for the disadvantage of the flash memory of the long time period required for the write operation. In the case where a central processing unit (CPU) processes data, since the write operation of the flash memory requires a long period of time, a latent period of a CPU is inevitably lengthened. When a large quantity of data is being written in the flash memory, the CPU cannot perform another process during the write operation.
Accordingly, a method has been utilized for apparently shortening the period of time required for the write operation by realizing a semiconductor memory device having a function of initially writing data in a nonvolatile semiconductor memory device called a page buffer, such as an SRAM in which a period of time required for the write operation is short, and then transferring batches of data from the nonvolatile semiconductor memory device to the flash memory. This releases the CPU from the data write operation on the flash memory which requires a long period of time, and thus can perform another process.
In this page buffer technique, an address in the page buffer is mirrored at an arbitrary address in the flash memory. Therefore, in a command sequence at the time of writing the data in the page buffer, a CPU issues a page buffer write command in the first cycle, inputs the number of batches of transfer data (hereinafter, referred to as “transfer data number”) in the page buffer in the second cycle, and inputs as an operand of the command a set of an address in the flash memory and a batch of data to be written in the page buffer in the third cycle. This operation in the third cycle is repeatedly performed in the later cycles until sets of an address and a batch of transfer data are input such that the number of the sets corresponds to the transfer data number input in the second cycle. A CPU issues a confirmation command in the last cycle.
By extracting the transfer data number from this command sequence in the second cycle and by extracting a transfer start address from the command sequence and storing the extracted transfer start address in the page buffer in the third cycle, a write state machine (which is a circuit for controlling internal operations of the memory device and is also referred herein to as “WSM”) uses the data, i.e., command information on the transfer data number, the transfer start address, etc., so as to perform a data transfer operation from the page buffer to the flash memory.
FIG. 9
shows an example of a primary structure of an address control circuit for use with the page buffer technique. In
FIG. 9
, when a command to transfer data is externally input to the WSM, the WSM controls an address control circuit
105
so as to start data transfer from the page buffer to the flash memory. This data transfer operation is further described in detail below.
As shown in
FIG. 9
, before starting the data transfer operation, the WSM controls the address control circuit
105
so as to store in a memory address register
100
the data transfer start address in the input command information via an external address pad A and store the transfer data number via a data pad D in a transfer data number register
102
.
Next, the WSM controls the memory address register
100
so as to transfer the stored data transfer start address of the flash memory to a memory address counter
101
via a transfer bus
120
connected between the memory address register
100
and the memory address counter
101
. This allows a flash memory array decoder
121
to perform a decode operation such that an address in a flash memory array to which data is transferred is set so as to be a data transfer start address while allowing a page buffer decoder
122
to perform a decode operation such that an address in the page buffer from which the data is transferred is set so as to be a transfer start address, i.e., a first address at which data to be written in the flash memory array is stored.
Next, a data counter
103
is reset so as to have an initial value. Then, the WSM accesses a memory cell selected according to the decoded address so as to read data from the page buffer and write the data in a memory cell at a transferee address in the flash memory.
This operation realizes a data write operation from the page buffer to the flash memory. When the data write operation from the page buffer to the flash memory is completed with respect to the decoded address, the WSM increments the memory address counter
101
such that an address of each of the page buffer and the flash memory is updated so as to be the next address (an address obtained by adding one bit to the current address). Similarly, the data counter
103
is incremented.
As described above, the WSM reads data at the updated address of the page buffer and writes the data in a memory cell corresponding to the updated address of the flash memory.
This operation is repeatedly performed. A comparison circuit
111
compares a value stored in the data counter
103
with a value latched by the data counter
103
which is the transfer data number in put from the WSM. When the comparison results in a match, the WSM detects that a final address is obtained, thereby completing the data transfer from the page buffer to the flash memory.
As devices using the page buffer technique described above, a semiconductor memory device which can reduce a decrease in data transfer rate by reducing overhead during data transfer (Japanese Laid-Open Patent Publication No. 11-85609, “SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANAGING DATA STORED THEREIN”), and a memory device which can realize high-speed write access to data along with low power consumption (Japanese Laid-Open Patent Publication No. 10-2

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