Multiplex communications – Network configuration determination – In a bus system
Reexamination Certificate
1999-10-25
2004-08-10
Duong, Frank (Department: 2666)
Multiplex communications
Network configuration determination
In a bus system
C370S389000, C370S395700, C370S419000
Reexamination Certificate
active
06775245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer control device and electronic equipment comprising the same.
2. Description of Related Art
An interface standard called IEEE 1394 has recently been attracting much attention. This IEEE 1394 has standardized high-speed serial bus interfaces that can handle the next generation of multimedia devices. IEEE 1394 makes it possible to handle data that is required to have real-time capabilities, such as moving images. A bus in accordance with IEEE 1394 can be connected not only to peripheral equipment for computers, such as printers, scanners, CD-R drives, and hard disk drives, but also to domestic appliances such as video cameras, VTRs, and TVs. This standard is therefore expected to enable a dramatic acceleration of the digitalization of electronic equipment.
The concept of IEEE 1394 is disclosed in various publications, such as “An outline of the IEEE 1394 High Performance Serial Bus” (
Interface,
April 1996, pages 1 to 10), “Bus Standers for PC Peripheral Equipment” (
Interface,
January 1997, pages 106 to 116), and “Real-Time Transfer Modes and Multimedia-Capable Protocols for IEEE 1394-1995 (FireWire)” (
Interface,
January 1997, pages 136 to 146). Texas Instruments' TSB12LV31 is known as a data transfer control device that conforms to IEEE 1394.
However, some technical problems have been identified with such a data transfer control device conforming to IEEE 1394, as described below.
That is to say, the current IEEE 1394 standard does make it possible to implement transfer speeds up to a maximum of 400 Mbps in practice, however, the presence of processing overheads forces the actual transfer speeds of entire system to be much slower. In other words, the firmware and application software running on a CPU require large amounts of time for processes such as preparing for transmitting data and reading in received data, which means it is not possible to implement high-speed data transfer overall, no matter how fast the data can be transferred over the IEEE 1394.
A particular problem lies in the fact that a CPU incorporated into peripheral equipment has a lower processing capability than the CPU incorporated into the host system, such as a personal computer. This makes the problem of processing overheads in the firmware and application software extremely serious. It is therefore desirable to provide techniques that are capable of efficiently solving this overhead problem.
SUMMARY OF THE INVENTION
The present invention was devised in the light of the above described technical problem, and has as an objective thereof the provision of a data transfer control device and electronic equipment using the same which are capable of reducing the processing overheads of firmware and application software, thus implementing high-speed data transfer within a compact hardware.
In order to solve the above described technical problems, a first aspect of the present invention relates to a data transfer control device for transferring data among a plurality of nodes that are connected to a bus, the data transfer control device comprising: link means for providing a service for transferring packets between nodes; storage means for storing packets, the storage means being randomly accessible; write means for writing to the storage means a packet that is being transferred from each of the nodes via the link means; and read means for reading out a packet that has been written to the storage means by an upper layer, and transferring-the packet to the link means.
With this aspect of the invention, packets that are being transferred from another node are written by the write means to a randomly accessible storage means. Packets that have been written to the storage means by an upper layer, such as firmware or application software, are read out by the read means and transferred to the link means. They are then transferred to other nodes Thus, in accordance with the present invention, the randomly accessible storage means for storing packets is interposed between the link means and the upper layers. This configuration makes it possible to store packets in any desired storage area within the storage means, regardless of the reception sequence or transmission sequence of the packets. This also makes it possible to divide the packets and store the resultant parts in a plurality of areas within the storage means.
In a second aspect of the present invention, the storage means is divided into a control information area for storing packet control information and a data area for storing packet data. This arrangement makes it possible to reduce the processing load on the firmware or application software in the upper layers, thus enabling an improvement in the actual transfer speeds of the entire system. It also simplifies the processing for reading packets from the storage means and writing packets to the storage means.
In a third aspect of the present invention, the storage means is divided into an area in which a packet is stored and a work area for a central processing unit. This reduces the storage capacity required of the local memory of the central processing unit; possibly even removing the need for local memory completely.
In a fourth aspect of the present invention, the control information area of the storage means is divided into a control information area for reception and a control information area for transmission. This arrangement makes it possible to read packet control information continuously from the control information area for reception and also write packet control information continuously to the control information area for transmission, simplifying the processing and reducing the processing load.
A fifth aspect of the present invention further comprises packet division means for writing packet control information to the control information area and writing packet data to the data area. This ensures that packet control information and packet data are automatically written to the control information area and data area, respectively, enabling a reduction in overheads in the upper layers, such as firmware.
In a sixth aspect of this invention, the link means generates tag information for delimiting at least control information and data of a packet, and also links the tag information to a packet, and the packet division means writes packet control information to the control information area and writes packet data to the data area, based on the tag information that has been linked to the packet. This arrangement makes it possible to store packet control information in the control information area and data in the data area, with a simple hardware configuration.
In a seventh aspect of this invention, the data area of the storage means is divided into a data area for reception and a data area for transmission. This arrangement makes it possible to read out receive data continuously from the data area for reception and write transmission data continuously to the data area for transmission, enabling a reduction in processing overheads on the upper layers.
In an eighth aspect of this invention, the data area of the storage means is divided into a data area for isochronous transfer and a data area for asynchronous transfer. This arrangement makes it possible to ensure that an isochronous packet has priority in processing, even if the isochronous packet has been transferred after an asynchronous packet. It is therefore possible to maintain the real-time capabilities of processing required for isochronous transfers.
In a ninth aspect of this invention, the data area of the storage means comprises a data area for asynchronous transfer; and the data area for asynchronous transfer is divided into a plurality of areas including first and second data areas for asynchronous transfer. This arrangement makes it possible to store data having different purposes in a plurality of areas within the data area for asynchronous transfer. In other words, control-related data such as command data and status data can be store
Ishida Takuya
Kamihara Yoshiyuki
Ogawa Takao
Duong Frank
Oliff & Berridg,e PLC
Seiko Epson Corporation
LandOfFree
Data transfer control device and electronic equipment does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data transfer control device and electronic equipment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer control device and electronic equipment will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3279678