Data transfer control circuit with a sequencer circuit and contr

Details Data transfer control circuit with a sequencer circuit and contr Data transfer control circuit with a sequencer circuit and contr

1994-04-28

1996-07-23

Kim, Matthew M.

Boots, shoes, and leggings

364DIG1, 364DIG2, 364243, 364251, 3642544, 395750, 395481, 348262, G06F 1200, G06F 118

Patent

active

055398910

ABSTRACT:
A power drain and noise reduction control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This control circuit substantially reduces the power drain by only powering up the portion of the circuit being written. Also noise which would otherwise be present on the data lines is reduced.

REFERENCES:
patent: Re34026 (1992-08-01), Duvvury et al.
patent: 3991408 (1976-11-01), Holmes, Jr. et al.
patent: 4024509 (1977-05-01), Elmer
patent: 4103338 (1978-07-01), Cizmic et al.
patent: 4115856 (1978-09-01), Labeye-Voisin et al.
patent: 4394726 (1983-07-01), Kohl
patent: 4418402 (1983-11-01), Heagerty et al.
patent: 4507730 (1985-03-01), Johnson et al.
patent: 4595978 (1986-06-01), Sheffield
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4894728 (1990-01-01), Goodman
patent: 4905189 (1990-02-01), Brunolli
patent: 4908789 (1990-03-01), Blokkum et al.
patent: 4918600 (1990-04-01), Harper, III et al.
patent: 5014238 (1991-05-01), McLeish et al.
patent: 5052049 (1991-09-01), Andros et al.
patent: 5056006 (1991-10-01), Acharya et al.
patent: 5115393 (1992-05-01), Kashiyama et al.
Mano, Computer System Architecture, 2nd Edition, 1982, pp. 21-35.
R. Davis et al., "Systolic Array Chip Matches the Pace of High-Speed Processing", Electronic Design, pp. 207-218, Oct. 31, 1984.
W. Hannaway, et al., "Handling Real-Time Images Comes Naturally to Systolic Array Chip", Electronic Design, pp. 257-266, Nov. 29, 1984.
L. Wallis, "Associative Memory Calls on the Talents of Systolic Array Chip", Electronic Design, pp. 217-226, Dec. 13, 1984.
Fisher, Allan L., et al., Architecture of a VLSI SIMID Processing Element, IEEE International Confernece on Circuits and Design, 1987, pp. 324-327.
van Rowermud, A. H. M., et al., A General-Purpose Programmable Video Signal Processor, ICCE 1989 VSP/Philips.
Chin, D., et al., The Princeton Engine: A Real-Time Video System Simulator, IEEE Transactions on Consumer Electronics, vol. 34, No. 2, May 1988, pp. 285-297.
Nakagawa, Shin-ichi, et al., A 50 ns Video Signal Processor, IEEE International Solid-State Circuits Conference, Digest of Technical Papers, vol. XXXII, 1989, pp. 168-169, 328.
Kikuchi, Kouichi, et al., A Single-Chip 16-Bit 25 ns Realtime Video/Image Signal Processor, IEEE ISSCC Digest of Technical Papers, vol. XXXII, 1989, pp. 170-171, 329.
Wilson, Stephen S., The Pixie-5000-A Systolic Array Processor, IEEE 1985, pp. 477-483.
Davis, Ronald, et al., Systolic Array Chip Matches the Pace of High-Speed Processing, Electronic Design, Oct. 21, 1984, pp. 207-218.
Hannaway, Wyndham, et al., Handling Real-Time Images Comes Naturally to Systolic Array Chip, Electronic Design, Nov. 15, 1984, pp. 289-300.
Smith, Jr., Winthrop W. et al., Systolic Array Chip Recognizes Visual Patterns Quicker Than A Wink, Electronic Design, Nov. 29, 1984, pp. 257-266.
Wallis, Lyle, Associative Memory Calls on the Talents of Systolic Array Chip, Electronic Design, Dec. 13, 1984, pp. 217-226.
Fisher, Allan L., et al, Real-Time Image Processing on Scan Line Array Processors, IEEE 1985, pp. 484-489.
Fisher, Allan L., Scan Line Array Processor For Image Computation IEEE 13th Annual International Symposium on Compu. Arch., Compu. Arch. news, vol. 14, No. 2, Jun. 1986, pp. 338-345.
Waltz, David I. Applications of the Connection Machine, IEEE Computer Magazine, Jan. 1987, pp. 85-97.
Webber, Donald M. et al., Circuit Simulation on the Connection Machine, 24th ACM/IEEE Design Automation Conference, 1987, pp. 108-113.
Hillis, W. Daniel, text book excerpt, The Connection Machine, The MIT Press series in artificial intelligence-Thesis (Ph.D.)-MIT, 1985, pp. 18-28.
Fountain, T. J., text book, Integrated Technology for Parallel Image Processing, "Plans for the CLIP7 Chip.", pp. 199-214, Chapter 13.
Gharaachorloo, Nader, et al., A Super Buffer: A Systolic VLSI Graphics Engine for Real-Time Raster Image Generation, 1985 Chapel Hill Conference on VLSI, pp. 285-305.

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