Data transfer control apparatus wherein an externally set value

Details Data transfer control apparatus wherein an externally set value Data transfer control apparatus wherein an externally set value

1995-11-13

1997-05-13

Asta, Frank J.

Boots, shoes, and leggings

395842, 395843, 395844, 364DIG1, G06F 1300

Patent

active

056301723

ABSTRACT:
To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

REFERENCES:
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patent: 4975832 (1990-12-01), Saito et al.
patent: 5077664 (1991-12-01), Taniai et al.
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patent: 5287471 (1994-02-01), Katayose et al.
patent: 5297292 (1994-03-01), Morimoto et al.
patent: 5497501 (1996-03-01), Kohzono et al.
Mitsubishi Electric User's Manual M37720S 2.13 DMAC.
Patent Abstracts of Japan, P-1093, Aug. 16, 1990, vol. 14., No. 381.

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