Data transfer control apparatus wherein a time value is compared

Details Data transfer control apparatus wherein a time value is compared Data transfer control apparatus wherein a time value is compared

1993-02-04

1996-07-09

Swann, Tod R.

Boots, shoes, and leggings

395494, 395550, 395842, 395848, 36424231, 36424234, 364DIG1, 3642428, 36424292, G06F 1300

Patent

active

055353622

ABSTRACT:
To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

REFERENCES:
patent: 4831523 (1989-05-01), Lewis et al.
patent: 5077664 (1991-12-01), Taniai et al.
patent: 5089955 (1992-02-01), Morinaga et al.
patent: 5297292 (1994-03-01), Morimoto et al.
Intel iAPX 86/88, 186/188 User's Manual, Hardware Reference, 1985, pp. 1-112-1-115 and FIGS. 1-95, 1-96.
Patent Abstracts of Japan, P-1093, Aug. 16, 1990 vol. 14, No. 381 (JP 2-143360, Jun. 1, 1990).
Mitsubishi Electric User's Manual M37720S 2.13 DMAC.

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