Data transfer control apparatus and method

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G06F 300

Patent

active

041124901

ABSTRACT:
An improved data transfer apparatus and method is fabricated by multiplexing at least a portion of the address of the peripherals on the data bus. Data transfer is simplified by adopting identical control timing for the read and write cycles, setting up address and data information early within a cycle and synchronizing the output of such information on the output busses coupled to the peripherals. Data transfer control signals may be encoded to simplify read and write input/output and memory operations. The advantage of such improvements permits reduce component count, pin requirements and gives rise to an ability to incorporate more system functions on a single chip.

REFERENCES:
patent: 3243781 (1966-03-01), Ehrmann et al.
patent: 3943495 (1976-03-01), Garlic
patent: 3967246 (1976-06-01), House
patent: 4004281 (1977-01-01), Bennett et al.

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