Pulse or digital communications – Cable systems and components
Reexamination Certificate
1999-09-16
2002-09-17
Vo, Don N. (Department: 2631)
Pulse or digital communications
Cable systems and components
C375S354000, C327S403000
Reexamination Certificate
active
06452976
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data transfer circuits and in particular to data transfer circuits synchronized with a clock signal to transfer data from a transmitting circuit to a receiving circuit.
2. Description of the Background Art
Conventionally it is well known that as a method of transferring data between semiconductor integrated circuit devices or internally in a semiconductor integrated circuit device, two data transfer lines arranged between a transmitting circuit and a receiving circuit are initially precharged to a same potential (e.g., precharged high) and one or the other data transfer line is then set low to transfer data “0” or “1”.
In this data transfer method, however, the two data transfer lines must initially be precharged high for each data transfer, disadvantageously resulting in an increased time required for precharging the data transfer lines and thus a decreased data transfer rate when the data transfer lines are increased in length and hence wiring capacitance and wiring resistance.
The inventors of the present invention have proposed a method of preventing reduction of data transfer rate by arranging three data transfer lines between a transmitting circuit and a receiving circuit. In this method, while two of the three data transfer lines are used to transfer data the remaining one data transfer line is precharged high, and in the subsequent data transfer period two of the three data transfer lines that are held high are used to transfer data, thereby preventing reduction in data transfer rate.
In this data transfer method, however, a data transfer line is precharged during data transfer and more current can be disadvantageously consumed than when a data transfer line is precharged conventionally after data transfer.
SUMMARY OF THE INVENTION
Therefore a main object of the present invention is to provide a data transfer circuit with high data transfer rate and reduced current consumption.
Briefly speaking of the present invention, three sets of an upstream signal line and a downstream signal line are provided between a transmitting circuit and a receiving circuit and a signal transmission circuit operating in synchronization with a clock signal is provided between each upstream signal line and each downstream signal line. A first select circuit selects two upstream signal lines of a first potential to set one of the two upstream signal lines of the first potential to a second potential to transmit data and also to precharge the remaining one upstream signal line to the first potential. Furthermore, a second select circuit selects two downstream signal lines of the first potential to connect the two downstream signal lines of the first potential to the receiving circuit and also to precharge the remaining one downstream signal line to the first potential. Furthermore, a third select circuit selects a downstream signal line to be set to the second potential and a downstream signal line to be precharged to the first potential for a subsequent data transfer period to connect the two selected downstream signal lines together via a connection circuit for a predetermined period. Thus, a downstream signal line to be set from the first potential to the second potential supplies an electrical charge to a downstream signal line to be precharged from the second potential to the first potential. Thus, the electrical charge can be effectively used to reduce current consumption.
Preferably the third select circuit includes a logic circuit associated with respective two of the three sets of an upstream signal line and a downstream signal line to output a control signal in response to the fact that the second potential has been attained by both the upstream signal line of one of the respective two sets of upstream and downstream signal lines and the downstream signal line of the other of the respective two sets of upstream and downstream signal lines, and a hold circuit holding a signal output from the logic circuit and outputting the signal in synchronization with a clock signal for a predetermined period of time, wherein the connection circuit includes a switching element associated with the logic circuit and connected between associated two downstream signal lines to conduct in response to the fact that an associated hold circuit has output the control signal. Thus the third select circuit and the connection circuit can readily be configured.
Still preferably a downstream signal line is larger in capacitance than an upstream signal line and in such example the present invention is particularly effective.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5339268 (1994-08-01), Machida
patent: 5765194 (1998-06-01), McBride
patent: 8-50788 (1996-02-01), None
patent: 10-241371 (1998-09-01), None
Ishikawa Masatoshi
Tanizaki Hiroaki
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