Data transfer circuit transferring 2-bit data through 4 data...

Details Data transfer circuit transferring 2-bit data through 4 data... Data transfer circuit transferring 2-bit data through 4 data...

1999-04-26

2002-10-08

Vo, Don N. (Department: 2631)

Pulse or digital communications

Equalizers

C375S257000

Reexamination Certificate

active

06463098

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data transfer circuits, and more particularly, to a data transfer circuit which transfers first and second data from a transmitting side circuit to a receiving side circuit.
2. Description of the Background Art
There are known conventional methods for internally transferring data in a semiconductor integrated circuit device, according to which a transmitting side circuit and a receiving side circuit are connected by a data line and voltage on the data line is changed by the transmitting side circuit for transferring data to the receiving side circuit. If data is thus transmitted by the voltage change on the single data line, however, noise affects the data line, which prevents the receiving side from determining the data to be received until voltage change equal to or greater than the level of the noise is obtained.
Therefore, in general, the transmitting side circuit and receiving side circuit are connected by two data lines provided in parallel, and the receiving side circuit is provided with a differential amplifier to amplify the potential difference between the data lines. According to this method, noise substantially equally affects the two data lines and the influence of the noise can be cancelled by taking the potential difference between the data lines. As a result, this method permits reception data to be determined with the voltage change between the data lines at a smaller level, faster data transfer than the data transfer method using the single data line can be achieved. This method however requires an equalizing operation before data transfer to bring the two data lines to the same potential level in order to compare the potentials of the two data lines.
FIG. 18
is a circuit block diagram of a conventional data transfer circuit using two data lines DL
1
and DL
2
and a sense amplifier SA, a kind of differential amplifier.
Referring to
FIG. 18
, in the data transfer circuit, the output nodes N
201
and N
202
of drivers
201
and
202
included in a data transmitting circuit TR and the input/output nodes N
203
and N
204
of sense amplifier SA included in the data receiving circuit are connected by data lines DL
1
and DL
2
, respectively, and an equalizer EQ is provided between data lines DL
1
and DL
2
.
Drivers
201
and
202
drive data lines DL
1
and DL
2
according to internal signals S
1
and S
2
based on transmission data, respectively. Equalizer EQ includes a P-channel MOS transistor
203
connected between data lines DL
1
and DL
2
, and P-channel MOS transistors
204
and
205
connected in series between data lines DL
1
and DL
2
. P-channel MOS transistors
203
to
205
receive together a data line equalize signal /DLEQ at their gates. Power supply potential Vdd is applied to the node between P-channel MOS transistors
204
and
205
. When signal /DLEQ attains an “L” level, P-channel MOS transistors
203
to
205
conduct so that data lines DL
1
and DL
2
are equalized to power supply potential Vdd.
Sense amplifier SA includes P-channel MOS transistors
211
and
212
and N-channel MOS transistors
213
to
215
as shown in FIG.
19
. P-channel MOS transistors
211
and
212
are connected between lines to power supply potential Vdd and input/output nodes N
203
and N
204
, respectively, and have their gates connected to the input/output nodes N
204
and N
203
, respectively. N-channel MOS transistors
213
and
214
are connected between input/output nodes N
203
and N
204
and node
205
, respectively and have their gates connected to input/output nodes N
204
and N
203
, respectively. N-channel MOS transistor
215
is connected between node N
205
and a line to a ground potential Vss and receives a sense amplifier activation signal &phgr;SE at its gate. The potentials of input/output nodes N
203
and N
204
become output signals VO
1
and VO
2
.
Sense amplifier SA is activated in response to sense amplifier activation signal &phgr;SE attaining an “H” level, and brings the node at the higher potential between input/output nodes N
203
and N
204
to power supply potential Vdd (“H”level) and brings the node at the lower potential to ground potential Vss (“L”level). Thus, the potential difference between input/output nodes N
203
and N
204
is amplified to power supply voltage Vdd.
FIGS. 20A
to
20
F are timing charts illustrating the operation of the data transfer circuit shown in
FIGS. 18 and 19
. Referring to
FIGS. 20A
to
20
F, in an initial state, data line equalize signal /DLEQ is at an “L” level so that equalizer EQ is activated, and the potentials of data lines DL
1
and DL
2
are equalized to an “H” level. Sense amplifier activation signal &phgr;SE attains an “L” level and sense amplifier SA is inactivated. Internal signals S
1
and S
2
are both at an “H” level.
At time t
0
, data line equalize signal /DLEQ attains an “H” level, which turns off P-channel MOS transistors
203
to
205
in equalizer EQ, so that data transfer is enabled. Subsequently, at time t
1
, one of internal signals Si and S
2
(S
1
in the figure) attains an “L” level. Driver
201
attempts to pull data line DL
1
to an “L” level, but the capacitance and resistance values of data line DL
1
are large, and therefore the potential of data line DL
1
gradually decreases.
At time t
2
, at which the potential difference between data lines DL
1
and DL
2
may be sensed and amplified by sense amplifier SA, sense amplifier activation signal &phgr;SE attains an “H” level, which turns on N-channel MOS transistor
215
in sense amplifier SA to activate sense amplifier SA. Thus, the potentials of data lines DL
1
and DL
2
, in other words the output signals VO
1
and VO
1
of sense amplifier SA rapidly attain an “L” level and an “H” level, respectively, so that the data transfer ends.
After the data transfer, at time t
3
, signals /DLEQ and &phgr;SE are pulled to an “L” level and signals S
1
and S” are pulled to an “H” level, thus equalizing data lines DL
1
and DL
2
to be ready for the next data transfer.
In the conventional data transfer circuit, however, after the equalizing operation is started at time t
3
, it takes a long period until the potentials of data lines DL
1
and DL
2
are completely pulled to the level of precharge potential Vdd, and during that period, the next data cannot be transmitted. If data lines DL
1
and DL
2
are long, the resistance and capacitance of the interconnections are large, and the time required for equalizing increases as a result. The interconnections are charged by equalizing, and therefore the power consumption increases if the data lines are longer.
SUMMARY OF THE INVENTION
It is therefore a main object of the present invention to provide a transfer circuit which permits the equalizing period and power consumption to be reduced.
Briefly stated, a transmitting circuit provides a potential difference between two data lines equalized to a first reference potential for transmitting first data and a potential difference to two data lines equalized to a second reference potential for transmitting second data. After the data transfer, a selecting circuit selects two data lines at potentials closer to the first reference potential as a first group and the other two data lines as a second group, and first and second equalizers equalize the first and second groups to the first and second reference potentials, respectively. The difference between the potential of a data line after the data transfer and the potential of the data line after the equalizing is smaller than the conventional case in which equalizing is performed regardless of the potentials of the data lines after the data transfer. Consequently, the equalizing period and power consumption can be reduced.
Preferably, the transmitting circuit pulls one of the two data lines equalized to the first reference potential to the second reference potential for transmitting the first data, and pulls one of the two data lines equalized to the second reference potential to the first reference

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