Data transfer circuit between a processor and a peripheral

Details Data transfer circuit between a processor and a peripheral Data transfer circuit between a processor and a peripheral

1986-12-19

1988-08-02

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 300

Patent

active

047617357

ABSTRACT:
A data transfer circuit for transferring data between a processor such as a personal computer and a peripheral. A command and data bus is connected between the processor and the data transfer circuit, and a peripheral bus is connected between the peripheral and the data transfer circuit. A counter is reset to zero and a random access memory is connected to the command and data bus when the data transfer cirucit is addressed. The counter increments by one responsive to each read or write command on the command and data bus such that the processor may read data from or write data to the random access memory without having to supply an address. A microcomputer based controller supplies addresses when data is read out of or written into the random access memory by the peripheral.

REFERENCES:
patent: 4386415 (1983-05-01), Chadra
patent: 4390964 (1983-06-01), Horky et al.

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