Data transfer circuit

Details Data transfer circuit Data transfer circuit

1997-12-22

2000-06-20

Nelms, David

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523009, G11C 800

Patent

active

060785454

ABSTRACT:
A data transfer circuit making it possible to enhance the operational efficiency of a CPU, decrease the burden imposed to software, and reduce the scale of hardware.
The data transfer circuit 10 is provided with a latch circuit 11 for latching signals EA, EB, EC indicating termination of the operation of a peripheral function portion, an operation result register 12 for storing operation results, an exclusive pointing register 13 designating a memory address for storing the contents of the operation result register 12 to a RAM, a selector 14 for selecting the exclusive pointing register 13 in response to the operation terminate signal EA, EB, EC, a selector 15 for selecting the operation result register 12 in response to the operation terminate signal EA, EB, EC, an OR gate 16 receiving the output of the latch circuit 11, a selector 17 for selecting a RAM address bus or the output signal from the selector 14, selectors 18, 19 for selecting the output signal, and a RAM 20.

REFERENCES:
patent: 4075691 (1978-02-01), Davis et al.
patent: 4442485 (1984-04-01), Ota et al.
patent: 4761735 (1988-08-01), Amy
patent: 5155853 (1992-10-01), Mitsuhira et al.
patent: 5297242 (1994-03-01), Miki
patent: 5497501 (1996-03-01), Kohzono et al.
patent: 5579531 (1996-11-01), Sugita

Affiliated with

Also associated with

Rating

Data transfer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transfer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1859022