Computer graphics processing and selective visual display system – Computer graphics processing – Attributes
Reexamination Certificate
2000-09-06
2003-12-30
Mancuso, Joseph (Department: 2697)
Computer graphics processing and selective visual display system
Computer graphics processing
Attributes
C345S564000, C345S571000
Reexamination Certificate
active
06670960
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to video-data processing and, more particularly, to the conversion of video data between different formats.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize devices that achieve increasingly complex functions at ever-increasing speeds. For many video applications, realizing higher-functioning devices requires moving data quickly between different physical memory spaces and/or different color-representation formats. Depending on the process used for moving such data, the usefulness and overall operability of the device can be significantly enhanced or detrimentally impaired.
Video communications is an example application involving video-data processing having an efficiency rating that depends heavily on how video data is moved between remotely-located terminals. A typical example application would involve first and second remotely-located terminals attempting to communicate video data over a channel such as a POTS (plain old telephone service) or ISDN line using a channel interface/driver which is appropriate for the channel. At the first terminal, video data is collected from a source in a format convenient for displaying the data at the first terminal. The collected data is then compressed into a new format and is then transmitted in the compressed format to the second terminal. Before the video data is compressed, it is converted to a format more adaptable for the compression. The second terminal then decompresses the data into another format convenient for its designated use. The efficiency rating for this type of video-data processing would therefore depend heavily on how the video data is handled as it is converted between formats and moved between remotely-located terminals.
Video-data processing applications have improved efficiency ratings using various approaches, some with particular emphasis on the video data compression formatting. A common compression format for video applications is JPEG, which generally uses a YCrCb (luma, chroma red and chroma blue) representation of the color space. However, computers typically display data using a RGB (Red, Green, Blue) color space. The RGB color space is an advantageous color space for display because commodity displays, such as LCDs and CRTs, are controlled via RGB inputs. JPEG uses 8×8 blocks to compress colors. JPEG compression often involves changing from a flat frame buffer in RGB to YCrCb prior to compression. JPEG decompression normally involves changing the YCrCb output from JPEG to the RGB color space for display purposes.
Previous attempts to increase the efficiency rating in JPEG applications have fallen short of keeping up with some of the high-speed applications required by recent systems. For example, such attempts have involved effective use and management of the busses interlinking the respective processors and the memory units, and the manner in which the processors retrieve each of the three RGB components in the flat frame buffer for respectively converting to each of the three YCrCb components. Other approaches for efficiently moving the data from a memory display buffer in RGB format to the DCT compression stage of a JPEG compression engine have involved use of a DMA with a full-line buffer for directly piping in the RGB components for conversion to each of the three YCrCb components. Each of these approaches has been relatively disadvantageous in the context of expense (as with the use of fill-line buffering with DMAs), power consumed, and/or the requisite bandwidth of the processor and memory.
SUMMARY
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements concerning the transfer of data between an RGB color space and a YCrCb color space memory in a manner that applies to, among others, the above-discussed applications.
A more particular aspect of the present invention is directed to a specific application wherein the YCrCb color space memory is used for communication with a DCT block-computation engine. In connection with this embodiment and application, aspects of the present invention are directed to methods and arrangements for transferring data between an RGB color space memory to a DCT block-computation engine so as to significantly increase throughput and decrease processor overhead.
In a specific example embodiment, a DMA function is optimized to fetch data from an external memory representing a RGB color space and to provide the data for a JPEG conversion while performing YCrCb color space conversion on the fly. Data is transferred from the RGB color space memory to a DCT block-computation engine adapted to process a YCrCb color space memory. The method includes providing the data for an RGB display screen area as a tile array having C columns and R rows of tiles, where one tile corresponds to sufficient RGB data for a DCT of at least one of a Cr data array and a Cb data array. Data is fetched at addresses in the tile array by accessing the data one tile at a time, and both the row within each tile and the tile within the tile array are tracked. The addresses are generated as a function of C, the tracked row and a tracked tile within the tile array. While the data is being fetched, the fetched data is used to fill buffers for the Y, Cr and Cb data arrays corresponding to the RGB display screen area.
Another embodiment is directed specifically to data transfer to the RGB color space memory from a DCT block-computation engine using, effectively, the reverse operation.
In other more specific implementations, the present invention is directed to use of a processor arrangement programmed and configured to handle the above-described data manipulations and to compute one of the addresses as a function of: the number of tiles in the array multiplied by TN, plus a count of the tracked row multiplied by a count of C multiplied by a constant, where TN corresponds to the tracked tile number within the tile array.
In yet another more specific implementation, the processor arrangement is further programmed and configured to compute one of the addresses as a function of: the number of tiles in the array multiplied by TN, plus a count of the tracked row multiplied by a count of C multiplied by a constant, and also as a function of a count within a word segment of a tile. For instance, the tile may be implemented using 16-word segments.
The above summary is not intended to provide an overview of all aspects of the present invention. Other aspects of the present invention are exemplified and described in connection with the detailed description.
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Chen Po-Wei
Mancuso Joseph
Zawilski Peter
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