Patent
1994-07-18
1997-05-06
Ellis, Richard L.
395250, G06F 13362, G06F 1336
Patent
active
056279680
ABSTRACT:
A data transfer apparatus which includes data devices which access a common, shared memory. Each data device is connected to a corresponding data buffer. A memory bus is connected to each of the data buffers and to the shared memory to allow data to be transferred between the data buffers and between the data devices and the shared memory via the data buffers. Data is transferrable between a transferring data device to a receiving data device by transferring data from the transferring data device to the data buffer corresponding to the transferring data device, from the data buffer corresponding to the transferring data device to the memory bus, from the memory bus to the data buffer corresponding to the receiving data device, and then from the data buffer corresponding to the receiving data device to the receiving data device. A data transfer controller controls the data buffers and the shared memory so that the shared memory does not transfer data onto the memory data bus when, during the transfer of data between the transferring data device and the receiving data device, data is being transferred between the data buffer corresponding to the transferring data device and the data buffer corresponding to the receiving data device via the memory bus.
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Okamoto Rikiya
Ozaki Tohru
Shimizu Seiya
Sugiyama Jun-ichi
Coulter Kenneth R.
Ellis Richard L.
Fujitsu Limited
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