1992-12-23
1995-04-18
Robertson, David L.
395250, 395200, G06F 1314
Patent
active
054086132
ABSTRACT:
A parallel processing system enabling a mixed transfer of packets of different lengths is achieved.
The data transfer apparatus in this parallel processing system comprises four address controllers. During the first data transfer the third address controller is used for sending and the first address controller is used for receiving data. During the second transfer, the fourth address controller is used for sending, and the second address controller is used for receiving.
When the first and second transfer operations are mixed, the first and second address controllers are selectively used during receiving, and the third and fourth address controllers are selectively used during sending. Each of the address controllers changes the address only after packet transfer is completed. The header of the packet contains a packet length field, which is interpreted to enable simultaneous, dynamic handling of plural packets of different lengths.
As a result, packets can be transferred without deadlocks occurring even when packets of different lengths are mixed.
REFERENCES:
patent: 4667287 (1987-05-01), Allen et al.
patent: 4769771 (1988-09-01), Lippmann et al.
patent: 5047917 (1991-09-01), Athas et al.
patent: 5315707 (1994-05-01), Seaman et al.
Dally et al., "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks", IEEE Transaction on Computers, vol. C-36, No. 5, May 1987.
Matsushita Electric - Industrial Co., Ltd.
Robertson David L.
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