Data transfer accelerating apparatus and method

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Details

364DIG1, 364DIG2, 364260, 3642624, 3642628, 3649462, 3649466, G06F 300, G06F 900

Patent

active

054559189

ABSTRACT:
In a computing system having a data source, a memory, and a central processing unit (CPU), data is transferred from the data source to the memory by first monitoring signals from the CPU to determine whether data transfer is desired. If data transfer is desired, an optimized instruction set is generated which is specifically designed to cause the CPU to carry out the data transfer in an optimal manner. This optimized instruction set is sent to the CPU and is executed thereby to transfer the data quickly and efficiently. An apparatus for carrying out the above method comprises a determiner, an instruction generator, and a coupling circuit. The determiner monitors address and control signals from the CPU to determine whether data transfer is desired. In response to a determination that data transfer is desired, the determiner generates a run control signal. The instruction generator receives from the data source the data to be transferred and a destination address in the memory in which the data is to be stored, and generates an optimized instruction set using this data and address. The instruction generator sends out this instruction set on its output. The coupling circuit receives the output of the instruction generator and, in response to the run control signal, sends the optimized instruction set to the CPU to allow the CPU to execute the instruction set to transfer data from the data source to the memory.

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