Data transfer abnormality processing system

Details Data transfer abnormality processing system Data transfer abnormality processing system

1981-06-23

1985-02-19

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900, G06F 1300

Patent

active

045009538

ABSTRACT:
A data processing system including a data transfer abnormality processing unit in which delays caused by the production of a data transfer abnormality signal during a data transfer cycle period are eliminated. A bus controller, a memory unit and one more data processing units are connected in parallel to a common bus which includes a data transfer abnormality signal line. The bus controller includes a data register which receives data from the common bus, delaying it for one cycle period before applying it to a transfer abnormality check circuit. The transfer abnormality signal produced by the transfer abnormality check circuit is stored in a transfer abnormality setting flip-flop in each data processing circuit with a clock pulse which is produced delayed with respect to a bus use permission signal.

REFERENCES:
patent: 3815099 (1974-06-01), Cohen et al.
patent: 4236203 (1980-11-01), Curley et al.
patent: 4300194 (1981-11-01), Bradley et al.

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