Data synchronizing system for multiple memory array processing f

Details Data synchronizing system for multiple memory array processing f Data synchronizing system for multiple memory array processing f

1996-03-18

1999-06-29

Harvey, David E.

Computer graphics processing and selective visual display system

Display driving control circuitry

Controlling the condition of display elements

348500, 348515, 3488453, 395551, H04N 504

Patent

active

059174820

ABSTRACT:
A data system includes a memory array operative together with a memory controller and a processor. The processor includes a control input which receives user commands. A plurality of data channels are provided for output and input of independent data streams from and to the memory array. A field rate clock provides field rate clock signals to the data channels. In several embodiments, each data channel includes a data stream synchronization system which includes a data queue for receiving a succession of data fields within the data channel and an ideal queue tightly coupled to and operatively associated with each data queue to provide a correct field reference for use in synchronizing the data queue. In an alternate embodiment, a plurality of data queues are tightly coupled to a common ideal queue. The system control apparatus is operative upon the common ideal queue or the ideal queues within each data channel to control the sequence of fields therein. Each data queue within each channel responds to and follows its associated ideal queue in the creation of its input data field.

REFERENCES:
patent: 5559999 (1996-09-01), Maturi et al.
patent: 5642171 (1997-06-01), Baumgartner et al.
patent: 5751280 (1998-05-01), Abbott et al.

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