Pulse or digital communications – Spread spectrum – Direct sequence
Patent
1989-10-30
1991-03-26
Olms, Douglas W.
Pulse or digital communications
Spread spectrum
Direct sequence
375118, H04L 700
Patent
active
050035584
ABSTRACT:
A synchronizing buffer which synchronizes data link data with the channel clock such that one character is transmitted onto the data link for each channel clock. The synchronizing buffer disclosed includes a first-in-first-out (FIFO) buffer which receives data characters from a data channel buffer, and outputs them onto the data link. When the channel clock is stopped, the synchronizing buffer circuit places idle characters on the data link with the proper disparity. When the channel clock restarts, the circuit synchronizes the sending of restarted data characters with the idle characters placed onto the link such that there is an intelligible string of characters on the data link at all times.
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IBM Technical Disclosure Bulletin, vol. 24, No. 8, 1/82, pp. 4404-4406, Asynchronous Multi-Clock Bidirectional Buffer Controller.
Gonzalez Floyd A.
Huseman Marianne
International Business Machines - Corporation
Olms Douglas W.
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