Data synchronizer lock detector and method of operation thereof

Details Data synchronizer lock detector and method of operation thereof Data synchronizer lock detector and method of operation thereof

1996-01-02

1997-12-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375324, H04L 700

Patent

active

056944403

ABSTRACT:
In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.

REFERENCES:
patent: 4768208 (1988-08-01), Cornett
patent: 5452331 (1995-09-01), Shihabi et al.

Affiliated with

Also associated with

Rating

Data synchronizer lock detector and method of operation thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data synchronizer lock detector and method of operation thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data synchronizer lock detector and method of operation thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-807822