Multiplex communications – Wide area network – Packet switching
Patent
1986-07-11
1988-06-07
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 94, H04J 326
Patent
active
047501715
ABSTRACT:
A high speed data bus is time division multiplexed into multiple logical timeslot channels. Each of these timeslot channels is dynamically allocated to multiple endpoints within the data communication system. Each of these timeslot channels is shared from multiple communication sessions by the endpoints using a CMSA/CD methodology for allocating asynchronously usage of the timeslot channels. Additionally, network terminators may be used which may support multiple logical sessions by dedicating a timeslot channel to a network terminator and having other multiple endpoints coupled to this network terminator by way of the shared channel access protocol. Multiple copies of the shared channel access protocol procedure are located at a network terminator to handle multiple usages of the peripheral bus by the network terminator.
REFERENCES:
patent: 3851104 (1974-11-01), Willard et al.
patent: 3924077 (1975-12-01), Blakeslee
patent: 3959594 (1976-05-01), Srivastava
patent: 4161786 (1979-07-01), Hopkins et al.
patent: 4210780 (1980-07-01), Hopkins et al.
patent: 4227178 (1980-10-01), Gergaud et al.
patent: 4234952 (1980-11-01), Gable et al.
patent: 4292623 (1981-09-01), Eswaran et al.
patent: 4330886 (1982-05-01), Fukuda et al.
patent: 4332985 (1982-06-01), Samuel
patent: 4390982 (1983-06-01), Williams et al.
patent: 4394757 (1983-07-01), Muzumdar et al.
patent: 4434421 (1984-02-01), Baker et al.
patent: 4450554 (1984-05-01), Steensma et al.
patent: 4463351 (1984-07-01), Chiarottino
patent: 4479213 (1984-10-01), Galand et al.
patent: 4494230 (1985-01-01), Turner
patent: 4506361 (1985-03-01), Kume
patent: 4514843 (1985-04-01), Albanese
patent: 4516205 (1985-05-01), Eing et al.
patent: 4516239 (1985-05-01), Maxemchuk
patent: 4524244 (1985-06-01), Faggin et al.
patent: 4530093 (1985-07-01), Akram et al.
patent: 4536875 (1985-08-01), Kume et al.
patent: 4538261 (1985-08-01), Kume
patent: 4542499 (1985-09-01), Bella et al.
patent: 4543574 (1985-09-01), Takagi et al.
patent: 4550402 (1985-10-01), Gable et al.
patent: 4564838 (1986-01-01), Boulogne et al.
patent: 4568930 (1986-02-01), Livingston et al.
patent: 4573045 (1986-02-01), Galin
patent: 4578789 (1986-03-01), Middleton et al.
"A Carrier Sense Multiple Access Protocol for Local Networks," Simon S. Lam, Department of Computer Sciences, University of Texas at Austin, Austin, Tex. 78712, pp. 21-32.
"Performance Analysis of Carrier Sense Multiple Access with Collision Detection," Fouad A. Tobagi et al., Computer Systems Laboratory, Stanford University, Stanford, Calif., pp. 245-259.
"Carrier Sense Subset Multiple Access System," L. P. West, IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, pp. 4811-4812.
"Decentralized Bus Architecture with Collision Retry," D. F. Bantz et al., IBM Technical Disclosure Bulletin, vol. 23, No. 2, Jul. 1980, pp. 858-861.
"Signalling in a Decentralized Subscriber Stage," Section (50A8), Bernd Lubben, University Hannover, International Switching Symposium, Paris, France, 7-11 May 1979, pp. 1241-1245.
"A Worldwide Integrated Service Communication System for Voice and Non-Voice," Keisuke Tomaru et al., Hitachi Ltd., Totsuka Works, Yokohama, Japan, pp. 45-47.
"Multiacess Protocols in Packet Communication Systems, " Fouada Tobagi, IEEE Transactions on Communications, vol. Com. 28, No. 4, pp. 468-488.
"Flexible Multiplexing Technique with Two Types of Packet for Circuit & Packet Switched Traffic," Hideo Miyahara et al., The Transactions of the IECE of Japan, vol. E64, No. 6, Jun. 1981, pp. 390-397.
AT&T DMI Specification, Apr. 1985.
CCITT, X.3, Packet Assembly/Disassembly Facility (PAD) in a Public Data Network.
CCITT, X.25, Interface Between Data Terminal Equipment (DTE) and Data Circuit Terminating Equipment (DCE) for Terminals Operating in the Packet Mode on Public Data Networks, pp. 100-189.
Intel, 8274, Multi-Protocol Serial Controller (MPSC), pp. 7-200-7-236.
Intel, iATC 2952, Integrated Line Card Controller, pp. 3-22-3-36.
Intel, 82C37A-5, Chomos High Performance Programmable DMA Controller, pp. 5-57-5-66.
Siemens, PBC Peripheral Board Controller, PEB 2050, Technical Description (Part I), pp. 1-25.
Siemens, Peripheral Board Controller, PEB 2050, Preliminary Technical Description (Part II), pp. 1-12.
Kedar Benjamin
Michalak Gerald P.
Olms Douglas W.
Tadiran Electronics Industries Ltd.
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