Multiplex communications – Wide area network – Packet switching
Patent
1988-09-02
1990-01-02
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 951, 370 99, H04L 1100, H04L 1116
Patent
active
048918040
DESCRIPTION:
BRIEF SUMMARY
The present invention relates to Data Switching Arrangements and more particularly but not exclusively to a switching arrangement between the line cards in a data communications system.
It is often found necessary in communications systems to transmit blocks of data from one line card to another within the system. A typical line card will have a capacity to cater for 8 ports of data from a corresponding number of terminals, each port operating at up to 16 Kbps in each direction. Thus in a proposed system having 64 data ports on several cards the overall rate would be 1 Mbps each way. It is also advantageous to use serial signalling as this reduces the number of interconnections required.
Standard high data link communication (HDLC) implementations are impractical for such a system as each block of data would have to be routed from the line card to an HDLC master controller, which would then re-transmit the data to its intended destinction. The minimum data rate for such a system is over 2 Mbps and thus has to be discarded due to the lack of high speed HDLC devices available and workload specification necessary from linecard processors.
A solution to the problem of linecard-to-linecard communication using fixed links or a Local Area Network (LAN) can be achieved but this is a costly option and therefore must be discarded.
It is an objective of the present invention to provide a switching arrangement which is practical and relatively inexpensive.
According to an embodiment of the present invention there is provided a time division multiplexed switching system comprising a plurality of data switching groups interconnected by a time division multiplexed data highway and central processing means, each of said switching groups comprising a plurality of data terminals connected to data interface means, the interface means comprising buffer storage means in respect of connected data terminals and control means responsive to data from the central processing means to transfer data to and from the data highway, each terminal in the system accessing the central processing means only when data therein is assembled for transmission, the central processing means allocating a transmit and/or a receive timeslot when so accessed and transferring data defining the or each time slot to the respective control means associated with the transmitting and receiving data terminals, the control means in each group causing data from the transmitting terminal to be held in the buffer storage means and to be segmented, each data segment in turn being associated with control data and transmitted to the data highway in the allocated time slot.
An embodiment of the present invention will now be described by way of example only with reference to the accompanying drawings in which;
FIG. 1 is a schematic view of an arrangement to conduct data switching including a data steering element according to the present invention;
FIG. 2 is a schematic view of the data steering element included in FIG. 1; and,
FIG. 3 illustrates a typical time frame definition for an arrangement according to FIG. 1.
FIG. 1 shows a schematic view of an arrangement to conduct data switching according to the present invention, a central processor unit (CPU) 1 is instructed that data at a terminal 3 is ready for transmission. The CPU 1 designates transmit and receive timeslots in a network highway 5, the necessary "setting-up" signalling being sent to the terminal 3 and a data interface means 9. In the embodiment described herein each data interface means 9 has ports 11 capable of connecting eight data terminals 3.
A typical sequence of data transmission between two terminals 3 would thus be: sending "set-up" signals to both the data interface means 9 associated with the transmitting and receiving terminals 3 through serial connections; 9' where it is buffered and subsequently controlled; timeslot and data is received by the interface means 9 in the corresponding receive timeslot. 3.
An important aspect of the invention is thus the data interface means 9 as shown in FIG.
REFERENCES:
patent: 4530093 (1985-07-01), Akram et al.
GEC Plessey Telecommunications Limited
Marcelo Melvin
Oglo Michael F.
Olms Douglas W.
Renfro Julian C.
LandOfFree
Data switching arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data switching arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data switching arrangement will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1388176