Data strobe buffer in SDRAM

Details Data strobe buffer in SDRAM Data strobe buffer in SDRAM

2000-06-30

2001-11-06

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S230080

Reexamination Certificate

active

06314050

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a memory device; and, more particularly, to a data strobe buffer applicable to a synchronous dynamic random access memory (SDRAM).
DESCRIPTION OF THE PRIOR ART
For achieving a high speed operation in a dynamic random access memory (DRAM), synchronous DRAMs (hereinafter, as is referred to “SDRAMs”) have been developed. The SDRAM operates in synchronization with an external clock signal. The SDRAM includes a single data rate (SDR) SDRAM, a double data rate (DDR) SDRAM and the like.
The SDR SDRAM operates in synchronization with rising edges of the external clock, so that one data is processed within one period of the external clock. On the contrary, the DDR SDRAM operates in synchronization with rising and falling edges of a data strobe signal, so that two successive data are processed within one period of the external clock. Therefore, compared with the SDR SDRAM, the DDR SDRAM achieves at least twice the operation speed without increasing frequency of the external clock. At this time, the data strobe signal is a signal instructing reception of a data to a controller.
In DDR SDRAM, the data strobe (hereinafter, as is referred to “DS”) signal maintains a high impedance state on idle state. In other words, the DS signal maintains the high impedance until the external clock is enabled. There is damping or fluctuation of the DS signal when the DS signal goes back to the high impedance state after being applied to a chip.
A data strobe buffer, which receives the DS signal as an input signal and outputs a pulse, generally includes two dynamic buffers. One generates a pulse on a rising edge of the DS signal ds. The other generates a pulse on a falling edge of the DS signal ds.
In the conventional data strobe buffer as mentioned above, both of two dynamic buffers always operate on a write operation. Accordingly, even if a small fluctuation of the DS signal occurs, an undesirable output is generated. Since an initial state of the DS signal is a high impedance state, if there is fluctuation, the data strobe buffer operates. The undesirable output of the data strobe buffer makes the chip rate higher. Also, the undesirable output of the data strobe buffer causes misoperation of the chip when an operational condition is tight.
A pulse generated at the rising edge does not influence on the operation of the chip. A pulse generated at a falling edge causes misoperation of the chip.
Not only DDR SDRAM but also all of SDRAMs using the data strobe signal have these disadvantages.
SUMMARY OF THE INVENTION
Therefore, it is an object to provide a data strobe buffer in SDRAM, the data strobe buffer preventing a chip from misoperating due to damping or fluctuation of a data strobe signal.
In accordance with an aspect of the present invention, there is provided to a data strobe buffer for a synchronous dynamic read only memory (SDRAM), including: a first dynamic buffer generating a first pulse at a rising edge of a data strobe signal; a second dynamic buffer generating a second pulse at a falling edge of the data strobe signal; and a block for generating an enable signal which is enabled in a range between a rising edge of an external clock signal and a logic high state of the second pulse, and providing the second dynamic buffer with the enable signal.


REFERENCES:
patent: 4802131 (1989-01-01), Toyoda
patent: 4970687 (1990-11-01), Usami et al.
patent: 6002613 (1999-12-01), Cloud et al.
patent: 09-306168 (1997-11-01), None
patent: 10199239 (1998-07-01), None
patent: 11288590 (1999-10-01), None

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