Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2001-05-09
2002-10-08
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S230010
Reexamination Certificate
active
06462977
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates generally to methods and apparatus for providing a matrix of uniquely addressable locations and, more particularly, to devices that may store data in a matrix of uniquely addressable locations that may be addressed using a reduced number of address bits.
2. Related Art
Several types of devices require unique locations to be addressed. Examples of these include, but are not limited to, devices that present data such as video displays, devices that may receive and record matrix data such as imaging arrays, and devices that may interconnect internally such as logic arrays. Another type of device, a conventional disk drive, also requires unique locations to be addressed. Conventional disk drives require mechanical manipulation of the disk to access data in a particular location.
Still another type of device which requires unique locations to be addressed is a device which may store and receive data such as a computer memory. Various portions of the following discussion will deal with memory devices such as computer memories. However, the teachings herein are not limited in this respect and may be applied to any type of device that requires unique addressing.
In the context of computer memories, since the advent of the first computer, it has been realized that memory devices for storing information are an essential element of a working computer. Many types of memories for computers have been developed, such as read-only memories (ROMs) and random-access memories (RAMs) as well as magnetic and optical data storage disks. These memories are accessed for read/write operations by the central processing unit (CPU) of the computer.
As computers have gotten smaller and faster, computer and memory unit designers have recognized that their memory devices likewise need to be smaller and operate faster. This has led to very competitive research and development of smaller, faster memory units.
The basic structure upon which present computer memories are based is the row/column array configuration. This structure has been very useful, not only in the field of computer memories but also as a model for conceptually dealing with data structures in the computer science art.
FIG. 1
is an example of a prior art memory array
1
. The memory array
1
includes several row address lines
2
and column address lines
3
. A memory cell is typically located at the intersection of a row address line and a column address line. The memory cells are used to store information, typically digital information. Examples of memory cells are a capacitor, a transistor device, a flip-flop, or an optical data storage device. As is well known, some memory cells store only a single bit while other types may be capable of storing a block of data such as typically referred to as a “word” or “byte”.
In order to access a particular memory cell in the memory array
1
, the CPU (not shown) must access both the row and the column corresponding to the location of the memory cell in the array. This entails sending a memory location address from the CPU to the memory array
1
. The address is then decoded by conventional means such as a multiplexer, and the correct memory cell of interest is then accessed. Thus, the location of each memory cell may be represented as n
r,c
where the r and c represent the row and column, respectively (with the first row and column being denoted as “0” as is conventional).
For example, in the 8×8 memory array
1
, if the CPU desired access to the memory cell at the intersection of the third row and the eighth column (n
2,7
) the CPU would have to send a binary row address of 010 to the row decoder
4
and a binary column address of 111 to the column decoder
5
. The row decoder
4
and column decoder
5
are typically implemented as multiplexers. The row decoder
4
converts the three bit row input to a binary representation of 00000100. This output is then transferred to the memory array
1
through hard wired connections between the output of the row decoder
4
and the memory array
1
. Thus, in order to access each row of the 8×8 memory array
1
, eight physical line connections (as well as the requisite multiplexer) must be included with the memory array
1
. Similarly, the column decoder
5
receives the address 111 and converts it to 10000000 leading to an additional 8 lines (and a second multiplexer) to be connected to the memory array
1
. Thus, a total of 16 physical line connections and two decoders are required in order to access each and every cell of the 8×8 memory array
1
. The interconnections and decoders require space on an integrated chip and therefore serve as a bottleneck when trying to reduce the physical size occupied by the memory array
1
and its supporting hardware.
When a memory array is configured in the manner described above, the number of address bits required to access the particular memory is determined by the size of the memory array. For example, addressing for a 64 cell, 8×8 memory array 1 requires at least 6 bits, 3 for the row and 3 for the column. Thus, an inherent relationship exists in essentially all conventional memory devices between the requisite number of address bits and the number of memory cells in the memory array
1
as shown in equation (1):
addresses=2
n
(1)
where n is the number of address bits. However, this equation is deceiving; it represents the number of bits the CPU must “send out” in order to access a particular memory cell of the memory array
1
. In actuality, the number of address bits received by the memory array
1
is equal to the number of physical line connections to the memory array
1
as discussed above. Thus, for the 8×8 array discussed above, the memory array
1
actually receives 16 address bits. This is more than double the number of address bits needed to represent each of the memory cells of the array. The transmission of these extra bits requires additional wiring and thus, increases the size and complexity of memory arrays.
Thus, for a square array containing 2
n
memory cells, 2×2
n/2
lines (i.e., 2
n/2
columns and 2
n/2
rows) must be supplied to and embedded within the array. For example, for an array of 4096 bits (i.e., 2
12
), 128 (i.e., 2×2
6
) lines are necessary, even though the lower limit of binary addresses required from the CPU is only 12—a full order of magnitude less than the row column scheme requires. This disparity grows exponentially as the array grows in size.
Other issues related to the amount of wiring required in conventional memory devices include the complex topology necessitated by the perpendicular passage of row and column lines past one another to reach their respective connections to the cell.
In addition to the size constraints imposed by the extra wiring of a memory array, implementing a memory unit as a two-dimensional array also has other size constraints. For instance, the physical layout of the memory unit imposes a size limitation. As the amount of memory needed has increased, many novel approaches for how to layout the memory device have been developed. For example, stacking the memory units on top of one another has been proposed. This allows for an increase in memory by increasing the volume of the memory unit without increasing the amount of surface area on a computer's mother board taken up by the memory. However, as the physical dimensions of computers have decreased, so has the available volume. Traditionally, each memory array in the stacked memory device must be individually addressed, which requires more hard wiring and address bits. Conceptually, each memory cell has a location of X
r,c,l
were r, c, and l are the row, column and layer, respectively of the stacked type of memory device. A novel approach to reducing the size of such a memory is disclosed in U.S. Pat. No. 5,623,160 where interconnections between the layers of integrated circuits are conducted by vertical pillars extending from a bottom layer to a top layer. Also, several dev
Tran Andrew Q.
Wolf Greenfield and Sacks, P.C.
LandOfFree
Data storage device having virtual columns and addressing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data storage device having virtual columns and addressing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data storage device having virtual columns and addressing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2993555