Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-05-25
2001-04-10
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S233100, C365S168000, C365S230060, C365S189120, C365S078000
Reexamination Certificate
active
06215728
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data storage device which stores data composed of a plurality of bits.
2. Description of the Related Art
Various kinds of data storage devices including also a data holding circuit such as a latch circuit which temporarily stores data have been proposed and put to practical use. However, most of these data storage devices stores one bit data by one storage element or one storage device. For example, in a D-type flip-flop, a signal level indicating a level “H” or a level “L” at a D input terminal is stored by applying clocks thereto. If the level “H” or the level “L” is being inputted to the D input terminal at a certain timing of rising up edges of the clocks, the level “H” or the level “L” is outputted from a Q-output terminal, and until a next timing of the rising up edge of the clocks, an output level at the Q-terminal is kept at the level “H” or the level “L” that is being outputted. As described above, one flip-flop can output only the two signal levels “H” or “L”. Accordingly, by corresponding the two signal levels to “1” or “0”, one bit data is stored in one storage circuit.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a data storage device which uses one storage circuit capable of taking two signal levels and can store plural bits of data.
To solve the above-described problems, a data storage device of the present invention storing plural bits of data comprises clock generating means for generating a reference clock signal having a predetermined reference cycle and at least one divided clock signal having a cycle (½)
n
(n: natural number) times the reference cycle; decoding means for selecting one of periods, based on contents of data inputted thereto, the periods being obtained by dividing the reference cycle and within each of which a signal level of the divided clock signal keeps constant; storage means for generating a cyclic pulse having the same cycle as the reference cycle and for starting to generate the cyclic pulse as a trigger timing, the trigger timing being a predetermined timing within one period selected by the decoding means; and output means for specifying output data based on a signal level of the reference clock signal and a signal level of the divided clock signal at the same phase timing as the trigger timing in terms of a cycle of the cyclic pulse.
In the data storage device which stores n bit data (n≧2), it is preferable that the clock generating means generates (n−1) pieces of the divided clock signals having different cycles.
The clock generating means may further generate a trigger clock signal obtained by dividing the above-described divided clock signal having the minimum cycle, and the storage means may be a single-shot type flip-flop which generates the cyclic pulse at a timing within one period selected by the decoding means, the timing being when the signal level of the trigger clock signal changes.
As the above-described storage means, an oscillation circuit may be used, which generates the cyclic pulse having the same cycle as the reference cycle at a predetermined timing in one period selected by the decoding means.
Furthermore, a plurality of D-type flip-flops can be used as the output means. In this case, cyclic pulses generated in the storage means are commonly supplied to clock input terminals of the respective D-type flip-flops. The reference clock signal is supplied to a D-input terminal of one of the D-type flip-fops. Furthermore, the divided clock signal is supplied to D-input terminals of other D-type flip-flops.
With such constitution, the reference cycle is divided every each period within which the signal level of the divided clock signal keeps constant. The decoding means selects one of the divided periods in accordance with the content data to be stored. As a result, within a specified period, the signal level of the reference clock signal and the signal level of the divided clock signal become constant. Accordingly, each period when the signal level of each clock signal becomes constant is made to correspond to the data to be stored. The storage means generates cyclic pulses at timings (trigger timings) within the selected period. The cycle of the pulses is equivalent to the reference cycle. Accordingly, in terms of the cycle of the pulses, the signal level of the reference clock signal is always kept to be constant. That is, the signal level of the reference clock signal becomes equal to the signal level at the trigger timing. Similarly, the signal level of the divided clock signal at the same phase timing as that of the trigger pulses are always equal to each other. In other words, that the storage means generates cyclically the pulses equivalent to the reference cycle at the trigger timing corresponds to the storage of the data. If the signal level of each clock signal at its phase timing is specified, the signal level of each clock signal at the time of generation of the first pulse, that is, the stored data, can be outputted.
REFERENCES:
patent: 5448524 (1995-09-01), Machida
patent: 5912859 (1999-06-01), Wuidart
Kanesaka & Takeuchi
Tran Andrew Q.
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